Abstract: A relay fault diagnosis device includes: at least one C-contact relay that has a common terminal, a normally open terminal and a normally closed terminal; a read-back circuit that is connected to the normally closed terminal of the relay; and a diagnostic section that outputs a test signal to the common terminal to diagnose a fault in the relay.

Abstract: An input/output apparatus for a PLC includes at least first and second sub-systems. In each sub-system, a DC-DC converter controls a voltage of an external power supply to a target voltage by switching a PWM signal, and a microcomputer is driven by a clock signal. In the microcomputer, a PWM signal generating unit generates the PWM signal and a frequency analyzing unit samples an inputted voltage at a cycle shorter than a cycle of the PWM signal, and analyzes the frequency of the inputted voltage. The frequency analyzing unit acquires a frequency of the PWM signal from the frequency of the inputted voltage, calculates a frequency of the clock signal, and outputs an abnormality-notifying signal when the frequency of the clock signal falls outside a prescribed range. An output voltage of the DC-DC converter of the first sub-system is inputted to the frequency analyzing unit of the second sub-system.

Abstract: A method of manufacturing a stator core includes punching out core members from an electrical steel sheet in three rows arrangement side by side along a width direction of the electrical steel sheet. Each of the core members has connecting projections. The connecting projections project radially outward from an outer periphery of the core member. The punched out core members are stacked to form the stator core. Each of the core members in two of the three rows arrangement have a connecting projection angled at a first angle from the width direction of the electrical steel sheet. Each of the core members in a third row having a connecting projection angled at a different second angle from the width direction of the electrical steel sheet.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.

Abstract: According to one embodiment of the present invention, this stator core manufacturing method has a punching step for punching core members, which each have a plurality of protruding sections for connection that protrude radially outwards from the outer peripheral section thereof, from a band-shaped electrical steel sheet, wherein: portions in the electrical steel sheet from which the core members are to be punched are arranged in three rows in the width direction of the electrical steel sheet; in any two of the three rows, the portions from which the protruding sections of the core members are to be punched are inclined at a first angle relative to the width direction of any of the electrical steel sheets; in the remaining one row, the portions from which the protruding sections of the core members are to be punched are inclined at a second angle relative to the width direction of the electrical steel sheet, said second angle being different from the first angle; and the core members are punched.

Abstract: A stator of a rotating electrical machine includes a stator core, plural stator coil groups constituting plural phases, plural pieces of interphase insulation paper for insulation of coils belonging to different phases, and plural connecting strips formed integrally with the interphase insulation paper pieces. Each interphase insulation paper piece has ends inserted between coil ends of unit coils belonging to an identical phase thereby to function as interphase insulation paper for insulation of coils belonging to the identical phase. Each interphase insulation paper piece for insulation of coils belonging to the different phases, functioning as the interphase insulation paper piece for insulation of coils of the identical phase, insulates between coil ends of the first unit coils of respective first and second series circuits constituting the inner circumference side phase and a coil end of the unit coil constituting the outer circumference side phase.

Abstract: A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

Abstract: A stator of rotating electrical machine includes a stator core and stator coils. The stator coils have n number (where n?6) unit coils, a first coil group and a second coil group. The unit coils of the first coil group include a first unit coil located nearest the first power supply terminal. The unit coils of the first coil group include a second unit coil. The unit coils of the first coil group include a third unit coil located third nearest the first power supply terminal and adjacent to the second unit coil of the second coil group. The unit coils of the second coil group include a third unit coil located third nearest the second power supply terminal and adjacent to the second unit coil of the first coil group.

Abstract: An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.

Abstract: A stator of a rotating electrical machine includes a stator core which is annular in shape, a plurality of stator coil groups constituting a plurality of phases, each-phase stator coil group being wound on the stator core and including a plurality of unit coils connected to each other, and a plurality of pieces of interphase insulation paper for insulation of coils belonging to different phases, disposed between coil ends of the unit coils belonging to different phases at both axial ends of the stator core, the interphase insulation paper pieces having ends which are inserted between the coil ends of the unit coils belonging to an identical phase, respectively.

Abstract: A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.

Abstract: A stator of rotating electrical machine includes a stator core and stator coils. The stator coils have n number (where n?6) unit coils, a first coil group and a second coil group. The unit coils of the first coil group include a first unit coil located nearest the first power supply terminal. The unit coils of the first coil group include a second unit coil. The unit coils of the first coil group include a third unit coil located third nearest the first power supply terminal and adjacent to the second unit coil of the second coil group. The unit coils of the second coil group include a third unit coil located third nearest the second power supply terminal and adjacent to the second unit coil of the first coil group.

Abstract: A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

Abstract: A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Abstract: A rotor for an electric rotating machine includes d-axis through holes located on respective d-axes, hollow shafts formed in both axial sides of a rotating shaft not inserted into a rotor core, presser plates mounted on both axial ends of the rotor core, cooling grooves formed in faces of the presser plates in contact with the rotor core, a plurality of presser plate refrigerant outlet holes in the presser plates, the presser plate refrigerant outlet holes of one of the presser plates having diameters different from diameters of the presser plate refrigerant outlet holes of one of the other presser plates, and a refrigerant channel formed so that a refrigerant supplied into one of the hollow shafts of the rotating shaft flows through the refrigerant channel and further through the hollow shaft wall hole of said one hollow shaft and the radial grooves of the respective presser plates.

Abstract: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.

Abstract: A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.