Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.

Abstract: A current driver, a common mode voltage monitoring circuit and a current compensator are provided to drive a twisted pair cable, which is made up of two signal lines coupled to a terminal bias voltage through respective terminal resistors. The common mode voltage monitoring circuit monitors a difference between a common mode voltage of the twisted pair cable and a supply voltage level for the current driver. And the current compensator is coupled to the twisted pair cable to compensate for an output current of the current driver in accordance with a result of monitoring performed by the common mode voltage monitoring circuit. If the current driver has decreased its current drivability due to a drop of the supply voltage level of the current driver or a variation in the common mode voltage of the twisted pair cable, then the current compensator compensates for the decrease. Thus, the current driver can continuously operate in a broad voltage range to supply a constant current.

Abstract: A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

Abstract: A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved.

Abstract: An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.

Abstract: An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.

Abstract: The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Abstract: The integrated circuit package of this invention includes a first integrated circuit chip and a second integrated circuit chip having a same function, wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus.

Abstract: The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Abstract: The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.

Abstract: A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed.

Abstract: In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.

Abstract: An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.

Abstract: In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.

Abstract: A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

Abstract: An electronic musical instrument for conducting an arpeggio performance of a stringed instrument capable of readily producing a pattern for the arpeggio performance as one likes, and also of conducting the arpeggio performance which is perceived as being less musically incompatible even if the player makes a mistake during a performance of allocating of pitch at the time of the arpeggio performance. A pattern for the arpeggio performance is produced adopting such a rule that a time axis is renewed when all the strings become silent, or such a rule that it is regarded as having the same timing while a pedal is kept depressed. When the arpeggio performance is conducted, even if a mismatch occurs between the string of the pattern and the string played for a pitch allocation, those strings are compulsively allocated together.

Abstract: A sewing apparatus for sewing an embroidery pattern that is larger than an embroidery region of an embroidery frame. The sewing apparatus divides the embroidery pattern into embroidery regions and causes the embroidery regions to overlap a predetermined width including a boundary line between adjacent embroidery regions.