Patents by Inventor Takashi Hiroi

Takashi Hiroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090226075
    Abstract: Disclosed herein are a circuit-pattern inspection apparatus, and a circuit-pattern inspection method, which are capable of making a highly sensitive defect judgment of an area including the most circumferential portion of a memory mat of a semiconductor chip formed on a semiconductor wafer.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 10, 2009
    Inventors: Takashi Hiroi, Takeyuki Yoshida, Naoki Hosoya, Toshifumi Honda
  • Patent number: 7532328
    Abstract: The disclosed subject matter is related to a circuit pattern inspection apparatus for detecting a gradual changing of defect expanding over a large area of the semiconductor wafer. In order to detect a gradual changing of a defect related condition expanding over a large area of the semiconductor wafer, comparison is made between dies on a wafer that are separated from each other by a distance of at least one die width. For example, when a value according to a difference between such dies exceeds a pre-determined value, an existence of the gradual changing can be confirmed.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: May 12, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiko Nara, Masaaki Nojiri, Kouichi Hayakawa, Takashi Hiroi
  • Patent number: 7521676
    Abstract: The present invention provides a mirror electron projection (MPJ) type (SEPJ type included) scanning electron beam apparatus that is capable of performing condition setup, and a method and apparatus for inspecting pattern defects with the scanning electron beam apparatus. A mirror electron projection type defect inspection apparatus, which comprises a charging device for emitting a charging electron beam, electron beam irradiation means for shedding a mirror electron projection electron beam onto an inspection region near which an electrical potential distribution is formed, detection means for detecting secondary electrons or reflected electrons generated from a surface and proximity of the specimen, and defect detection means for detecting a defect by processing a mirror image signal that is detected by the detection means, includes irradiation condition optimization means for optimizing charging electron beam irradiation conditions.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 21, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hirohito Okuda, Takashi Hiroi, Masaki Hasegawa, Shigeya Tanaka
  • Publication number: 20080302964
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined changed state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 11, 2008
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Patent number: 7457453
    Abstract: A pattern inspection apparatus including: an image detecting part for detecting a digital image of an object substrate; a display having a screen on which the digital image of the object substrate and/or a distribution of defect candidates in a map form are displayable; an input device for inputting information of a non-inspection region to be masked on the object substrate by defining a region on the screen on which said distribution of defect candidates is displayed in a map form; a memory part for storing coordinate data, pattern data or feature quantity data of the non-inspection region to be masked on the object substrate inputted on the screen by the input device; and a defect judging part in which the digital image detected by the image detecting part is examined in a state that a region matching with a condition stored in the memory part is masked and a defect is detected in a region other than said masked region.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: November 25, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Publication number: 20080285841
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Application
    Filed: July 10, 2008
    Publication date: November 20, 2008
    Inventors: Michio NAKANO, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima
  • Patent number: 7439504
    Abstract: A pattern inspection method and apparatus in which a charged particle beam is irradiated onto a surface of a specimen on which a pattern is formed, plural sensors simultaneously detect secondary particles emanated from the surface of the specimen by the irradiation, signals outputted from each sensor of the plural sensors which simultaneously detect the secondary particles are added, an image of the surface of the specimen on which the pattern is obtained from the added signals, and the image is processed to detect a defect of the pattern.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: October 21, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hiroi, Asahiro Kuni, Masahiro Watanabe, Chie Shishido, Hiroyuki Shinada, Yasuhiro Gunji, Atsuko Takafuji
  • Patent number: 7420167
    Abstract: An apparatus and method for electron beam inspection with projection electron microscopy, is constructed so as to allow correction of changes in focus offsets due to changes in the electrically charged state particularly during inspection. The apparatus includes: a focus measure sensor unit; a focus measure calculation unit which calculates focus measure from the multiple image signals converted by the focus measure sensor unit; a focus position calculation unit which calculates the height of a confocal plane conjugate to the plane of convergence of a planar electron beam by an objective lens, on the basis of the calculated focus measure, and then calculates the focus position of the objective lens on the basis of the calculated height of the confocal plane; and a focus position correction unit which corrects the focus position of the objective lens according to the calculated focus position of the objective lens.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: September 2, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hirohito Okuda, Takashi Hiroi, Hiroshi Makino
  • Patent number: 7421110
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: September 2, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Michio Nakano, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima
  • Patent number: 7417444
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Publication number: 20080174772
    Abstract: The disclosed subject matter is related to a circuit pattern inspection apparatus for detecting a gradual changing of defect expanding over a large area of the semiconductor wafer. In order to detect a gradual changing of a defect related condition expanding over a large area of the semiconductor wafer, comparison is made between dies on a wafer that are separated from each other by a distance of at least one die width. For example, when a value according to a difference between such dies exceeds a pre-determined value, an existence of the gradual changing can be confirmed.
    Type: Application
    Filed: October 15, 2007
    Publication date: July 24, 2008
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Masaaki Nojiri, Kouichi Hayakawa, Takashi Hiroi
  • Publication number: 20080099675
    Abstract: An inspection apparatus includes an irradiation optical system for irradiating an inspection target with an electron beam, a scanning unit for scanning an irradiation position in the X direction and the Y direction, an electrification control electrode for controlling secondary electrons or reflected electrons generated on the inspection target by the irradiation with the electron beam, a sensor for detecting the secondary electrons or the reflected electrons, an A/D converter for sequentially converting the signals into digital image signals from an irradiation start point-in-time of the electron beam, an addition circuit for creating a detection image by adding the digital image signals from a first set point-in-time to a second set point-in-time on each pixel basis, and an image processing circuit for judging a defect by comparing the detection image with a reference image of a circuit pattern formed on the inspection target.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 1, 2008
    Inventors: Takashi Hiroi, Hiroshi Miyai, Hirokazu Ito, Michio Nakano
  • Publication number: 20080078933
    Abstract: A method and apparatus for assessing a height of a specimen includes an electron beam unit having an electron beam source, lenses, a table for setting a specimen and controllable in a height direction, and a detector, and a height detection system for detecting height of the specimen set on the table while the specimen is irradiated by an electron beam. The height detection system further includes an illumination system, a collection system, first and second detectors, a device configured to receive output signals from the first and second detectors while the specimen is irradiated by the electron beam and to generate a comparison signal from the output signals, wherein the comparison signal is responsive to the height of the specimen.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 3, 2008
    Inventors: Masahiro WATANABE, Takashi Hiroi, Maki Tanaka, Hiroyuki Shinada, Yasutsugu Usami
  • Publication number: 20080067381
    Abstract: A semiconductor wafer inspection tool and a semiconductor wafer inspection method capable of conducting an inspection under appropriate conditions in any one of an NVC (Negative Voltage Contrast) mode and a PVC (Positive Voltage Contrast) mode is provided. Primary electrons 2 are irradiated onto a wafer to be inspected 6 and the irradiation position thereof is scanned in an XY direction. Secondary electrons (or reflected electrons) 10 from the wafer to be inspected 6 are controlled by a charge control electrode 5 and detected by a sensor 11. An image processor converts a detection signal from the sensor 11 to a detected image, compares the detected image with a predetermined reference image, judges defects, an overall control section 14 selects inspection conditions from recipe information for each wafer to be inspected 6 and sets a voltage to be applied to the charge control electrode 5.
    Type: Application
    Filed: June 7, 2007
    Publication date: March 20, 2008
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Takashi Hiroi, Kenji Tanimoto, Yuko Sasaki, Hiroshi Makino
  • Publication number: 20080063257
    Abstract: An apparatus for processing a defect candidate image, including: an imager for taking an enlarged image of a specimen; an image processor for processing the image taken by the imager to detect defect candidates existing on the specimen and classify the detected defect candidates into one of plural defect classes; a memory for storing information of the defect candidates including the images of the defect candidates and the classified defect class data outputted from the image processor; and a display unit having a display screen for displaying information stored in the memory, wherein the display unit displays an image of the defect candidates together with the defect class data stored in the memory and the displayed defect class data is changeable on the display screen, and the memory changes the stored defect class data of the displayed defect candidate to the changed defect class data.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Inventors: Takashi HIROI, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Publication number: 20080056559
    Abstract: An apparatus for processing a defect candidate image, including: a scanning electron microscope for taking an enlarged image of a specimen by irradiating and scanning a converged electron beam onto the specimen and detecting charged particles emanated from the specimen by the irradiation; an image processor for processing the image taken by the scanning electron microscope to detect defect candidates on the specimen and classify the detected defect candidates into one of plural classes; a memory for storing output from the image processor including images of the detected defect candidates; and a display unit which displays information stored in the memory and an indicator, wherein the display unit displays a distribution of the detected and classified defect candidates in a map format by distinguishing by the classified class, and the display unit also displays an image of a defect candidate stored in the memory together with the map which is indicated on the map by the indicator.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 6, 2008
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Patent number: 7329889
    Abstract: An electron beam apparatus including a table which mounts a specimen and is movable in three dimensional directions, an electron beam optical system irradiating an electron beam onto a specimen and for detecting a secondary electron emanated from the specimen by the irradiation of the electron beam, and a surface height detection system for detecting height of the surface of the specimen mounted on the table. A focus control system controls a relative position between a focus position of the electron optical system and the table in accordance with information of the height, and an image processing system obtains an image from the detected secondary electron and processes the obtained image to detect a defect on the surface of the specimen.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: February 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Watanabe, Takashi Hiroi, Maki Tanaka, Hiroyuki Shinada, Yasutsugu Usami
  • Publication number: 20080002876
    Abstract: In a pattern inspecting apparatus, images of places which can be expected to be the same pattern are compared with one another. However, a comparison of images obtained by different stage scans and the occurrence of a place capable of being inspected only once lead to a deterioration in the performance of detecting various error defects and an area incapable of being inspected, respectively. For solving this problem, defects detected in a high sensitivity condition are regarded as defect candidates and a critical threshold value, used as a boundary to detect a smaller value as a defect, of a defect candidate portion is obtained by an image processing circuit or an image of the defect candidate portion is obtained by processing with software. Further, the critical threshold value thus obtained is compared with plural threshold values, thereby permitting plural inspection results to be obtained in a single inspection.
    Type: Application
    Filed: September 11, 2007
    Publication date: January 3, 2008
    Inventors: Takashi Hiroi, Masahiro Watanabe, Maki Tanaka, Asahiro Kuni, Chie Shishido, Hiroshi Miyai, Yasuhiko Nara, Mitsunobu Isobe
  • Publication number: 20070269101
    Abstract: A pattern inspection apparatus including: an image detecting part for detecting a digital image of an object substrate; a display having a screen on which the digital image of the object substrate and/or a distribution of defect candidates in a map form are displayable; an input device for inputting information of a non-inspection region to be masked on the object substrate by defining a region on the screen on which said distribution of defect candidates is displayed in a map form; a memory part for storing coordinate data, pattern data or feature quantity data of the non-inspection region to be masked on the object substrate inputted on the screen by the input device; and a defect judging part in which the digital image detected by the image detecting part is examined in a state that a region matching with a condition stored in the memory part is masked and a defect is detected in a region other than said masked region.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 22, 2007
    Inventors: Takashi HIROI, Masahiro WATANABE, Chie SHISHIDO, Aritoshi SUGIMOTO, Maki TANAKA, Hiroshi MIYAI, Asahiro KUNI, Yasuhiko NARA
  • Patent number: 7292327
    Abstract: The disclosed subject matter is related to a circuit pattern inspection apparatus for detecting a gradual changing of defect expanding over a large area of the semiconductor wafer. In order to detect a gradual changing of a defect related condition expanding over a large area of the semiconductor wafer, comparison is made between dies on a wafer that are separated from each other by a distance of at least one die width. For example, when a value according to a difference between such dies exceeds a pre-determined value, an existence of the gradual changing can be confirmed.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: November 6, 2007
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiko Nara, Masaaki Nojiri, Kouichi Hayakawa, Takashi Hiroi