Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. An active region has a plurality of gate trenches. An interlayer dielectric (ILD) has a sloped region and a planar region. A metal contact hole has a sidewall aligned to the sloped region of the ILD. A metal contact is provided in the metal contact hole and couples the active region.

Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

Abstract: In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate (e.g., an n-type semiconductor region, epitaxial layer, etc.).

Abstract: In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate, e.g., an n-type semiconductor region, epitaxial layer, etc.).

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Abstract: A step-up/down DC-DC converter and switching control circuit are described. According to one implementation, a switching control circuit generates on/off signals of a first switching device supplying a current to a voltage conversion inductor of a step-up/down DC-DC converter and a second switching device receiving a current from the inductor. The switching control circuit includes an error amplifier circuit, an inverter amplifier circuit, a waveform generator circuit, a first voltage comparator circuit, a second voltage comparator circuit, and a voltage generator circuit. An inverting reference voltage supplied to the inverting amplifier circuit is set to an electric potential so as not to fall below a highest electric potential of triangle waves supplied to the first and second voltage comparator circuits.

Abstract: A step-up/down DC-DC converter and switching control circuit are described. According to one implementation, a switching control circuit generates an on/off signal of a first switching device supplying a current to a voltage conversion inductor of a step-up/down DC-DC converter and a second switching device receiving the current from the inductor. The switching control circuit includes an error amplifier circuit, an inverting amplifier circuit, a waveform generator circuit, a first voltage comparator circuit, a second voltage comparator circuit, and a peak-value detector circuit. The peak-value detector circuit detects a peak value of triangle waves generated at the waveform generator circuit and supplies a voltage corresponding to the peak value to the inverting amplifier circuit as a reference voltage.

Abstract: The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.

Abstract: A step-up DC-DC converter has a switching element for feeding current to an inductor; a rectifier connected to the output side of the inductor; and a control circuit performing on/off control of the switching element, based on an output voltage and a voltage corresponded to the inductor current. The control circuit further has a first voltage comparator circuit detecting fall of the output voltage down to the first reference voltage; a second voltage comparator circuit detecting that the inductor current reached a predetermined current value; and a voltage generation circuit generating a voltage inversely proportional to an input voltage and feeds the voltage, as a second reference voltage, to the second voltage comparator circuit. The switching element turns on, when the output voltage fell down to the first reference voltage, whereas the switching element turns off, when voltage proportional to the inductor current rose up to the second reference voltage.

Abstract: A step-up/down DC-DC converter and switching control circuit are described. According to one implementation, a switching control circuit generates on/off signals of a first switching device supplying a current to a voltage conversion inductor of a step-up/down DC-DC converter and a second switching device receiving a current from the inductor. The switching control circuit includes an error amplifier circuit, an inverter amplifier circuit, a waveform generator circuit, a first voltage comparator circuit, a second voltage comparator circuit, and a voltage generator circuit. An inverting reference voltage supplied to the inverting amplifier circuit is set to an electric potential so as not to fall below a highest electric potential of triangle waves supplied to the first and second voltage comparator circuits.

Abstract: A step-up/down DC-DC converter and switching control circuit are described. According to one implementation, a switching control circuit generates an on/off signal of a first switching device supplying a current to a voltage conversion inductor of a step-up/down DC-DC converter and a second switching device receiving the current from the inductor. The switching control circuit includes an error amplifier circuit, an inverting amplifier circuit, a waveform generator circuit, a first voltage comparator circuit, a second voltage comparator circuit, and a peak-value detector circuit. The peak-value detector circuit detects a peak value of triangle waves generated at the waveform generator circuit and supplies a voltage corresponding to the peak value to the inverting amplifier circuit as a reference voltage.

Abstract: A DC-DC converter including, an inductor; and a driving switching element for performing switching to a flow path to flow an electric current through the inductor; wherein the DC-DC converter drives the driving switching element by PWM control using a PWM control pulse to convert a direct-current input voltage supplied from a direct-current power source and to output a direct-current voltage having a piece of electric potential different from that of the direct-current input voltage, and wherein the DC-DC converter drives the driving switching element by the PWM control under a first condition, and the DC-DC converter makes the driving switching element be in an on-state continuously while the output direct-current voltage is lower than a desired level under a second condition.

Abstract: Provided is a DC-DC converter comprising: a drive switching element so that a current flows to an inductor, the drive switching element being driven by a PWM control pulse or a PFM control pulse, wherein a direct-current input voltage supplied from a direct-current power source is converted so as to output the converted direct-current voltage having a different potential, and wherein a PWM control is performed when a load is larger than a predetermined value and a PFM control is performed when the load is smaller than the predetermined value, the DC-DC converter further comprising: a pulse width regulation section to regulate the PWM control pulse so as not to have a pulse width smaller than a predetermined pulse width, at least when the PFM control is switched to the PWM control.

Abstract: Disclosed is a direct-current power supply device, including: an inductor; a switching element to intermittently supply a current to the inductor; an output terminal connected to an external unit; a rectifying element connected between the inductor and the output terminal; a PFM comparator to generate a first pulse signal having a pulse width corresponding to a voltage proportional to an output current of the external unit; a duty control circuit to generate a second pulse signal by controlling a pulse width of an oscillation signal having a predetermined frequency in response to an externally-supplied current control signal; a logic circuit configured to output the second pulse signal during a period when the first pulse signal is at a predetermined level; and a drive circuit to generate a drive signal for driving the switching element based on the second pulse signal.

Abstract: The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.