TRANSISTOR DEVICE HAVING A PILLAR STRUCTURE
In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.
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This Application claims priority to and the benefit of U.S. Provisional Application No. 62/608,462, filed on Dec. 20, 2017, entitled, “A Transistor Device Having a Pillar Structure,” which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThis description relates to a transistor device having a pillar structure.
BACKGROUNDSome transistor devices may be subject to, for example, a parasitic bipolar transistor that can be triggered and can prevent turn-off of the transistor device. The parasitic bipolar transistor can be triggered by self-biasing in the base of the parasitic bipolar transistor due to substrate current. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features.
SUMMARYIn at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
The transistors described here can have source region defined so that a parasitic bipolar device (e.g., NPN bipolar transistor device) included within the transistor is prevented from being activated in an undesirable fashion. Specifically, a transistor structure, as described herein, can be configured to prevent turn-on of a parasitic bipolar device included in the transistor structure when the transistor structure is being turned-off. The activation of the parasitic bipolar device can be referred to as latch-up and can be triggered in response to self-biasing of the base in the parasitic bipolar device in response to a substrate current. The transistor devices described herein can be configured with structures that reduce the base resistance while maintaining a desirable on-resistance. Thus reducing, or eliminating, undesirable latch-up conditions associated with a parasitic bipolar device when the transistor structure is being turned-off.
For example, a source region of a transistor, as described herein, can have a pillar structure included within the source region that has a conductivity type opposite a conductivity type of the source region. As a specific example, in a trench metal-oxide-semiconductor field effect transistor (MOSFET) device, the surface of a silicon mesa (mesa top and mesa sidewall) can have an N-type conductivity, and the middle (e.g., middle portion) of the silicon mesa can include a pillar, which can have P-type conductivity. The P-type conductivity pillar (e.g., P-pillar) can be in contact with a body region of the MOSFET device. These pillar structures within the transistor, for example, can be used to reduce base resistance while maintaining a desirable on-resistance of the transistor. Accordingly, undesirable latch-up conditions associated with a potential parasitic bipolar device can be reduced, or eliminated, when the transistor is being changed to an off state.
The channel and mesa top of a conventional structure can be connected by a P-type high concentration body layer that does not operate in a desirable fashion as a channel. Therefore, when trying to reduce the body, in order to reduce the base resistance, the effective channel area is decreased. In contrast, transistors with the pillar structures described herein can have a relatively shallow body region without affecting, in an adverse fashion, performance in the channel region. The transistors described herein are configured to prevent parasitic bipolar device turn-on by, for example, reducing the base resistance of the parasitic device without channel area penalty (e.g., reduced channel area).
The mesa 120 includes a source region 130, a body region 160, and at least a portion of an epitaxial layer 170. The source region 130 and the epitaxial layer 170 can each be of a first conductivity type. The body region 160, which is disposed between (e.g., disposed vertically between) the source region 130 and the epitaxial layer 170, is of a second conductivity type. The first conductivity type is opposite that of the second conductivity type. In some implementations, the transistor 100 (and other transistors disclosed herein) can be associated with only a few unit cells. In some implementations, the first conductivity type can be an N-type conductivity (e.g., an N-type dopant (e.g., phosphorus (P), arsenic (As), antimony (Sb))) and the second conductivity type can be a P-type conductivity (e.g., a P-type dopant (e.g., boron (B), aluminum (Al), gallium (Ga))). In some implementations, the first conductivity type can be a P-type conductivity and the second conductivity type can be an N-type conductivity. The conductivity types described herein, although discussed as being associated with a particular type of dopant, can be reversed to form different devices (e.g., P-channel devices, N-channel devices).
A channel (or channels) can be defined within the source region 130 when the transistor 100 is in an on-state (based on an applied voltage to the electrodes 110A, 110B). Current can flow between the source conductor 180 and the drain conductor 190 when the transistor 100 is in an on-state.
A source conductor 180 is in contact with the source region 130. The source conductor 180 is insulated from the electrodes 110A, 110B by the respective dielectric layers 112A, 112B. The epitaxial layer 170 can be disposed on a substrate 180, and a drain conductor 190 can be in contact with the substrate 180. The vertical direction (which is the depth direction or the height direction) in this implementation is aligned along the y-axis. The horizontal direction (which is the width direction or the lateral direction) in this implementation is aligned along the x-axis. The length direction in this implementation is aligned along the z-axis. As oriented in
As shown in
Without the pillar 140, the transistor 100 can be subject to latch-up of a parasitic bipolar device that can prevent the transistor 100 from turning off in a desirable fashion. The parasitic bipolar device can include, for example, the source region 130 (e.g., emitter), the body region 160 (e.g., base), and the epitaxial layer 170 (e.g., collector). In some implementations, the pillar 140 can be used to reduce the resistance of a path to a body contact (not shown in
Because the transistor 100 includes the pillar 140, even in implementations where the width of the mesa 120 is relatively narrow (e.g., narrowed to a sub-micron width), the on-resistance of the transistor 100 can be maintained at a desirable level. Also, the base resistance of the parasitic NPN structure (e.g., the body region 160) can be decreased using the pillar 140 without an undesirable affect on the channel of the transistor 100 (e.g., decrease in channel area).
The pillar 140 and the source region 130 are in a top portion of the mesa 120. The pillar 140 of the second conductivity type is disposed in the mesa region 130 so that a first portion 130A and third portion 130C (which can be referred to as side portions) of the source region 130 is disposed lateral to the pillar 140. The pillar 140 is disposed between the first portion 130A and the third portion 130C. A second portion 130B (also can be referred to as a top portion) of the source region 130 is disposed above the pillar 140. The first portion 130A can be contiguous with (e.g., can be in contact with) the second portion 130B. The second portion 130B can be contiguous with (e.g., can be in contact with) the third portion 130C.
In this implementation, the pillar 140 is aligned along a vertical axis A1 (or plane). The vertical axis A1 intersects (in order from top to bottom) the second portion 130B of the source region 130, the pillar 140, the body region 160 (which is below the pillar 140), and the epitaxial layer 170. As shown in
The pillar 140 is at least partially surrounded by the source region 130. In this implementation, a top surface 141 of the pillar 140 is covered, at least on three sides (top and sidewalls) by the source region 130. In this implementation, a top surface 141 of the pillar 140 is covered by (e.g., entirely covered by, surrounded by) the source region 130 (e.g., the second portion 130B). The side surfaces 142, 143 of the pillar 140 are covered by (e.g., surround by) the source region 130 (e.g., the first portion 130A and third portion 130C).
As shown in
The top surface of the mesa 120 (e.g., the top surface of the source region 130) is also disposed above (e.g., vertically above) a top surface of each of the electrodes 110A, 110B and the dielectric layers 112A, 112B. The portion 130B of the source region 130 is disposed above (e.g., vertically above) a top surface of each of the electrodes 110A, 110B and the dielectric layers 112A, 112B.
A bottom 144 of the pillar 140, which is at an interface between the body region 160 and the pillar 140, is illustrated by a dashed line. The bottom 144 of the pillar 140 is approximately the location of the transition in different dopant concentrations between the body region 160 and the pillar 140. The bottom 144 of the pillar 140 is below a top surface of each of the electrodes 110A, 110B. An interface between the body region 160 and the epitaxial layer 170 is also below (e.g., vertically below) a top surface of each of the electrodes 110A, 110B.
As shown in
The respective thicknesses B1, B2, B3 of each of the portions 130A, 130B, 130C can be the same. In some implementations, the thickness B2 of the portion 130B can be less than the thickness B1 and/or thickness B3. In some implementations, the thickness B2 of the portion 130B can be greater than or equal to the thickness B1 and/or thickness B3. The thickness B1 can be equal to the thickness B3 so that the pillar 140 is centered (e.g., aligned in a centered fashion) within the mesa 120 and centered (e.g., aligned in a centered fashion) within the source region 130.
As shown in
In some implementations, the pillar 140 can have a width C1 that is less than a combined width of the widths B1, B3 (of the portions 130A, 130C). Accordingly, the width B1, or the width B3 can be less than half of the width C1. In some implementations, the pillar 140 can have a width C1 that is greater than or equal to the combined width of the widths B1, B3 (of the portions 130A, 130C). Accordingly, the width B1, or the width B3 can be greater than or equal to half of the width C1.
The pillar 140 may have a shape different than the rectangular cross-sectional shape (e.g., profile) shown in
As noted above, the body region 160 and the pillar 140 are the same conductivity type. In this implementation, the body region 160 and the pillar 140 have the second conductivity type. Accordingly, the pillar 140 can be referred to as a pillar portion of a region of the second conductivity type, and the body region 160 can be referred to as a body portion of the region of the second conductivity type.
As shown in
As shown in
As shown in
As shown in
The body region 160 and body contact 162 and the pillar 140 are the same conductivity type (e.g., second conductivity type). Accordingly, the pillar 140 can be referred to as a pillar portion of a region of the second conductivity type, and the body region 160 and body contact 162 can be referred to as first and second body portions of the region of the second conductivity type.
In some implementations, the body contact 162 can have a different dopant concentration than the body region 160 and/or the pillar 140. In some implementations, the body contact 162 can have a dopant concentration greater than that of the pillar 140, and the body region 160 can have a dopant concentration than that of the body region 160. In some implementations, the body contact 162 can function as a body contact for the transistor 100. This body contact implementation will be described in more detail below.
As shown in
As shown in
The various cross-section views illustrated in
An example plan view of a transistor 200 that can include various combinations of the cross-sections illustrates in
A body pitch E is also illustrated in
Perspective views that combine the concepts discussed in connection with
As shown in
Under reverse bias and avalanche conditions, charge flows through the channel region in the body region 160 to the body contact 162 (which functions as a body contact (or body diode)). The inclusion of the pillar 140 in the mesa 120 results in an overall cross-sectional area of material on a path to body contact 162 that lowers the resistance in the channel region (which is in the body region 160). In other words, the cross-sectional area of the combination of the pillar 140 and the body region 160 allows for relatively more current to flow to the body contact 162 (especially in under reverse bias and avalanche conditions). This can result in the latch-up voltage of the parasitic bipolar device being increased. Without the pillar 140, the cross-sectional area of the base region of the parasitic bipolar (which corresponds with the body region 160) would be decreased and the transistor 300 would be more susceptible to latch-up of the parasitic bipolar device.
As shown in
As shown in
In some implementations, because the portion 130C of the source region 130 is continuous, a channel region can be formed within the transistor 300 even in the body contact region 302 of the transistor 300. This can result in a decrease in on-resistance of the transistor 300 (compared with implementations without continuity of the source region 130 in the body contact region 302).
As shown in
After formation of the dielectric layer 604, a P-type implant process (e.g., a 2-sided Boron implant at 30 degrees) can be performed (depicted by arrows P1) as shown in
An N-type implant process can be performed as shown in
In some implementations, the ratio of a length of the source region and the body contact can be controlled by mask patterns to target a particular on-resistance and/or potential latch-up (bipolar device turn-on) voltage. In some implementations, a rapid thermal anneal (RTA) (e.g., a rapid thermal oxidation (RTO)) process is performed to further define the source region 630 as shown in
As shown in
The method can include forming a first trench and a second trench in a semiconductor region such that a mesa region is defined between the first trench and the second trench (block 710). In some implementations, the mesa region can be less than a micron in width.
A dielectric layer can be formed along a sidewall of each of the first trench and the second trench (block 720), and an electrode can be formed in each of the first trench and the second trench (block 730). The electrode can be a gate electrode and can include, for example, a polysilicon material.
A body region of a first conductivity type is formed in the mesa region (block 740). The body region can be formed in an epitaxial layer on a substrate. The epitaxial layer can have a second conductivity type opposite the first conductivity type.
A source region of a second conductivity type is formed in a top portion of the mesa region such that a first portion of the source region is disposed lateral to a pillar of a first conductivity type and a second portion of the source region is disposed above the pillar (block 750). The first portion can be a side portion of the source region. The second portion can be a top portion of the source region. In some implementations, the pillar and the source region can have a profile similar to that shown in, for example,
The method can also include forming a body region, using an implant process, along a portion of the mesa such that body contact region is formed. In some implementations, the body region in the body contact region can have a cross-sectional profile similar to those shown in, for example,
It will be understood that, in the foregoing description, when an element, such as a layer, a region, a substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
Claims
1. An apparatus, comprising:
- a first trench disposed in a semiconductor region and including a gate electrode;
- a second trench disposed in the semiconductor region;
- a mesa region disposed between the first trench and the second trench;
- a source region of a first conductivity type disposed in a top portion of the mesa region;
- an epitaxial layer of the first conductivity type;
- a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type, the second conductivity type being different than the first conductivity type; and
- a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to, and in contact with the pillar and a second portion of the source region is disposed above, and in contact with the pillar.
2. The apparatus of claim 1, wherein the pillar is aligned along a vertical axis, the vertical axis intersects the second portion of the source region, the pillar, and the body region.
3. The apparatus of claim 1, wherein the source region includes a third portion, the pillar is disposed between the first portion of the source region and the second portion of the source region.
4. The apparatus of claim 1, wherein the mesa has a first width and the pillar has a second width, the second width being approximately half of the first width.
5. The apparatus of claim 1, further comprising:
- a source conductor in contact with the source region and defining an Ohmic contact.
6. The apparatus of claim 1, wherein the mesa region has a length aligned along a longitudinal axis orthogonal to a vertical axis along a height of the mesa region and orthogonal to a width of the mesa region,
- the pillar of the second conductivity, the first portion of the source region, and the second portion of the source region intersect a first cross-sectional plane at a first location along the length of the mesa region,
- the pillar is in contact with a body contact at a second cross-sectional plane at a second location along the length of the mesa region.
7. The apparatus of claim 6, wherein the pillar is disposed vertically between the body region and the body contact.
8. The apparatus of claim 6, wherein the body contact has a width equal to the width of the mesa region.
9. The apparatus of claim 1, wherein the mesa region has a length aligned along a longitudinal axis orthogonal to a vertical axis along a height of the mesa region and orthogonal to a width of the mesa region,
- the first portion of the source region is discontinuous along the length of the mesa region.
10. The apparatus of claim 1, wherein the mesa region has a length aligned along a longitudinal axis orthogonal to a vertical axis along a height of the mesa region and orthogonal to a width of the mesa region,
- the first portion of the source region has a discontinuity at a body contact along the length of the mesa region.
11. The apparatus of claim 10, wherein the second portion of the source region is continuous along a length of the mesa region below the discontinuity of the first portion of the source region at the body contact.
12. The apparatus of claim 1, further comprising:
- a source conductor in contact with the source region;
- a drain conductor; and
- a substrate in contact with the epitaxial layer and disposed between the source conductor and the drain conductor.
13. The apparatus of claim 1, wherein the mesa region has a top surface disposed above a top surface of the electrode disposed in the first trench.
14. An apparatus, comprising:
- a first trench disposed in a semiconductor region and including a gate electrode;
- a second trench disposed in the semiconductor region;
- a mesa region disposed between the first trench and the second trench;
- a source region of a first conductivity type disposed in a top portion of the mesa region; and
- an epitaxial layer of the first conductivity type,
- the mesa region including a first region of a second conductivity type at a first cross-section along the mesa region and a second region of the second conductivity type at a second cross-section along the mesa region, the second conductivity type being different than the first conductivity type,
- the first region of the second conductivity type having a different shape than the second region of the second conductivity type,
- both the first region of the second conductivity type and the second region of the conductivity type having a pillar portion and a body region below the pillar portion,
- the first region including a body contact above the pillar portion.
15. The apparatus of claim 14, wherein the body contact is excluded from the second region.
16. The apparatus of claim 14, wherein the first region of the second conductivity type has a surface area greater than a surface area of the second region of the second conductivity type.
17. The apparatus of claim 14, wherein the body contact has a bottom portion with a length that is less than a length of a top portion of the body contact.
18. A method, comprising:
- forming a first trench and a second trench in a semiconductor region such that a mesa region is defined between the first trench and the second trench;
- forming a dielectric layer along a sidewall of each of the first trench and the second trench;
- forming an electrode in each of the first trench and the second trench;
- forming a body region of a first conductivity type in the mesa region; and
- forming a source region of a second conductivity type in a top portion of the mesa region such that a first portion of the source region is disposed lateral to, and in contact with a pillar of a first conductivity type and a second portion of the source region is disposed above, and in contact with the pillar, the second conductivity type being different than the first conductivity type.
19. The method of claim 18, further comprising:
- forming a body contact, using an implant process, along a portion of the mesa.
20. The method of claim 18, further comprising:
- blocking an implant during the formation of the source region such that the first portion of the source region has a discontinuity in a body contact region.
Type: Application
Filed: Apr 3, 2018
Publication Date: Jun 20, 2019
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (Phoenix, AZ)
Inventors: Takashi OGURA (Oizumi-machi), Mitsuru SOMA (Higashimatsuyama), Dean E. PROBST (West Jordan, UT), Takashi HIROSHIMA (Ota-city), Peter A. BURKE (Portland, OR), Toshimitsu TANIGUCHI (Aizuwakamatsu)
Application Number: 15/943,914