Patents by Inventor Takashi Hosaka

Takashi Hosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6544852
    Abstract: In a method for forming a self-aligned contact in a MOS-type semiconductor device, a gate electrode film is deposited on a semiconductor substrate and an insulating film is deposited on the gate electrode film. The gate electrode film and the insulating film are then patterned such that the portion of the device where the two films are located is higher than any other regions of the device. A side wall insulating film is formed on the side wall of the gate electrode and the insulating film. Source and drain regions are formed in the face of the substrate using the patterned gate electrode film as a mask. A conductor film is then deposited on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film. A flattening film is then deposited to flatten the surface of the semiconductor, and a region of the flattened film and the conductor film which is above the gate electrode film is etched, using a photoresist film as a mask.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: April 8, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Publication number: 20030052417
    Abstract: To minimize the area of a chip-size package provided with balls, an equilateral triangle defined by pitches between balls is used as a basic shape, and a chip is formed into a shape in which the equilateral triangles are arranged side by side.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 20, 2003
    Inventor: Takashi Hosaka
  • Publication number: 20030045033
    Abstract: It is intended to provide high quality IC packages with the same size as that of IC chips. In a step of covering semiconductor chips with a resin for protection thereof, the resin is also allowed to adhere onto an opposite side of the substrate on which the semiconductor chips are mounted.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventor: Takashi Hosaka
  • Publication number: 20030042594
    Abstract: It is intended to provide a configuration of a semiconductor package used for manufacturing a small high-quality semiconductor package with a flat lead and to provide a method of manufacturing a lead frame. The semiconductor package with a flat lead is formed to have a lead frame with its lead portion made thinner than its foot portion.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventor: Takashi Hosaka
  • Patent number: 6528354
    Abstract: In the manufacture of semiconductor devices in which a plurality of semiconductor chips are mounted to a substrate, warping of the substrate is prevented by covering a first surface of the substrate with a first resin layer, covering a second surface of the substrate opposite the first surface with a continuous film and covering the continuous film with a second resin layer. Stresses applied to the substrate by the first and second resin layers cancel each other out to prevent warping of the substrate. The second resin layer is removed by peeling the.continuous film, so that individual chip die may be removed by dicing the substrate.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 4, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 6475897
    Abstract: A semiconductor device, such as an IC package, having the same size as an IC chip and having improved qualities is manufactured at a low cost by a particular manufacturing method. The semiconductor device has stepped-projection bumps bonded to electrode pads on a semiconductor substrate in which a semiconductor element is formed. A column portion and a portion in a horizontal portion of each stepped-projection bump are exposed while the other portion of the bump is covered with a protective material. When windows of the protective material corresponding to the column portions are formed, the windows are patterned by using a masking material based on a photoetching method, and the protective material is removed by etching.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: November 5, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Publication number: 20020068375
    Abstract: There is provided a semiconductor module that can be easily manufactured and has a photosensitive element. A minute unevenness portion is formed over the entirety or a portion of the region except for a light receiving portion in a mold for forming a module. Thus, a minute unevenness portion is formed over the entirety or a portion of the region except for the light receiving portion on the surface of the module. This module is immersed into a solution containing a light shielding material to deposit the film containing the light shielding material in the unevenness portion. The module in which the film is deposited is thermal-treated, and thus the module in which the film containing the light shielding material is deposited over the entirety or a portion of the region except for the light receiving portion can be manufactured.
    Type: Application
    Filed: September 27, 2001
    Publication date: June 6, 2002
    Inventor: Takashi Hosaka
  • Publication number: 20020066937
    Abstract: There is provided a semiconductor module that can be easily manufactured and has a photosensitive element. A method of manufacturing the module comprises the steps of: adhering a sheet made of a light shielding material onto a module having a photosensitive element; breaking the sheet by a protrusion of a light receiving portion in a module surface through which light reaches the photosensitive element; and covering at least a portion of a region except for the light receiving portion.
    Type: Application
    Filed: September 27, 2001
    Publication date: June 6, 2002
    Inventor: Takashi Hosaka
  • Patent number: 6329274
    Abstract: For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: December 11, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Naoto Inoue, Kenji Aoki, Takashi Hosaka
  • Patent number: 5352626
    Abstract: Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation Layer is formed on regions that include the steps or side walls of the grooves.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: October 4, 1994
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5293061
    Abstract: Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation layer is formed on regions that include the steps or side walls of the grooves.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: March 8, 1994
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5234863
    Abstract: The present invention relates to a method of forming contacts in contact holes used in the semiconductor devices. The object of the present invention is to flatten the contacts to contact holes of a size smaller than 1 .mu.m in order to decrease the contact resistance in the contact holes. After a contact hole is formed on an P.sup.+ diffused layer, a polycrystalline (or amorphous) silicon film containing P-type impurities is formed by a chemical vapor-phase deposition method to fill the contact hole. Then, the contact hole only is filled with the polycrystalline silicon film by an etch-back method. Contact to an N.sup.+ diffused layer is subsequently formed in the same manner using a silicon film containing N-type impurities, followed by an upper wiring. Since polycrystalline silicon film is formed by the vapor-phase deposition method maintaining good step-covering property, the contact hole is sufficiently filled.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: August 10, 1993
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5210043
    Abstract: A process for producing a semiconductor device having a structure in which a silicide film is in contact with an impurity diffusion layer inside a semiconductor substrate through a contact hole, in that, after the formation of the silicide film, an element of the same conductivity type as that of the impurity diffusion layer is implanted by ion implantation in the vicinity of the interface between the silicide film and the impurity diffusion layer through the silicide film.
    Type: Grant
    Filed: September 26, 1990
    Date of Patent: May 11, 1993
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5149669
    Abstract: An isolation method which enables bird's beaks to be reduced and which also permits a reduction in the number of defects is disclosed. A masking layer which masks against field oxidation comprises a polycrystalline silicon film covered with silicon nitride films. The surface of the semiconductor substrate which is not masked by the masking layer is subjected to an oxidation treatment to form an element isolation region.
    Type: Grant
    Filed: March 4, 1988
    Date of Patent: September 22, 1992
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5118636
    Abstract: A process for manufacturing a trench isolation device is mainly comprised of steps of forming a trench in an impurity ion doped region in a semiconductor substrate after the impurity ion doped region has been formed by ion implantation. The ion energy for the ion implantation is charged from a low energy level to a high energy level, or vice versa, in order to provide a uniform vertical doping profile or a graded vertical doping profile. By this method, field dope layers completely surround the trench in the trench isolation device.
    Type: Grant
    Filed: November 9, 1988
    Date of Patent: June 2, 1992
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5030588
    Abstract: A method of making a semiconductor device having a film resistive element. A resistive film is deposited over a substrate formed with a first contact hole open to an under-layer electrode region disposed in or on the substrate. The resistive layer is selectively etched to form the film resistive element and at the same time to leave portion of the resistive film disposed in and around the first contact hole. An inter-layer insulating film is then formed over the substrate. The inter-layer insulating film is selectively etched to form a second contact hole open to the film resistive element and at the same time to remove at least portion of the inter-layer insulating film disposed in and around the first contact hole. An over-layer electrode pattern film is formed in contact with the resistive film left in the first and second contact holes.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: July 9, 1991
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 5001527
    Abstract: In the step of forming a thin insulation film with the thickness of less than 1,000 .ANG. on the polycide electrode and wiring after formiung the polycide electrode and wiring, a semiconductor device having preferable insulation performance and high reliability is formed by using a silicon oxide film (SiO.sub.2) formed by a chemical vapor deposition process using a dichlorosilane (SiH.sub.2 Cl.sub.2) gas and a nitrous oxide (N.sub.2 O) gas under a reduced pressure of from 0.1 mbar to 2 mbar and at a temperature from 700.degree. C. to 950.degree. C. as the insulation film.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: March 19, 1991
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka
  • Patent number: 4954867
    Abstract: A semiconductor device uses a high melting point metal such as tungsten, molybdenum, etc. at its gate electrode and wirings for higher operation speed. In particular, the top and the side of the gate electrode and wirings are covered by a layer of silicon oxynitride whereby the gate electrode and the wiring are protected from oxidation and deterioration which may be cause by heat treatment in an oxidative atmosphere and ion implantation.
    Type: Grant
    Filed: June 1, 1988
    Date of Patent: September 4, 1990
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Hosaka