Patents by Inventor Takashi Iida

Takashi Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050237998
    Abstract: An audio decoding apparatus comprises packet order change control means, comprising packet rearranging storage means capable of storing one or a plurality of received packets, for outputting the packet which has been sent out in the earliest time from a transmission side, out of the packet received this time and the packets stored in the packet rearranging storage means, on the basis of order information related to the received packet and order information related to the packets stored in the packet rearranging storage means as well as storing in the packet rearranging storage means the packets excluding the outputted packet out of the received packet and the packets stored in the packet rearranging storage means; and an FIFO jitter buffer for sequentially storing the packets outputted from the packet order change control means as well as outputting the stored packets in the order inputted.
    Type: Application
    Filed: February 2, 2004
    Publication date: October 27, 2005
    Inventors: Kozo Okuda, Mika Kirimoto, Takashi Iida
  • Publication number: 20050048843
    Abstract: A plug for electric connectors comprises a housing 34 and a cap 36. The housing 34 comprises an insertion space 71 that allows a noise filter 35 to be fitted onto lengths of electric wire 32 before the housing is covered by the cap 36 after contacts 30 are latched. The cap 36 comprises a wall surface 75 provided in a direction, in which the noise filter 35 comes off. And, the plug for electric connectors is assembled in the order of (1) a step of latching the contacts 30 on a plug portion 31a of the housing 34, (2) a step of fitting the noise filter 35 onto the lengths of electric wire 32 that are connected to the contacts 30 and disposed within the housing 34, and (3) a step of covering the housing 34 with the cap 36 and forming a wall surface 72 in a direction, in which the noise filter 35 comes off.
    Type: Application
    Filed: December 19, 2002
    Publication date: March 3, 2005
    Inventor: Takashi Iida
  • Publication number: 20050017357
    Abstract: A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.
    Type: Application
    Filed: June 28, 2004
    Publication date: January 27, 2005
    Inventors: Takashi Iida, Tatsuya Nagata, Seiji Miyamoto, Toshihiro Matsunaga
  • Patent number: 6786746
    Abstract: A squib connector assembly for energizing a gas producer to make it ignite, the squib connector assembly comprising a first component for supporting a male electrical connector element; a second component for supporting a female electrical connector element engageable with the male electrical connector element; and a short-circuit element selectively switchable between a short-circuit position to electrically short-circuit the male electrical connector element and a non-short-circuit position. A flat-plate-like noise filter having electromagnetic wave absorbing material is arranged between the first component and the short-circuit element, so as to allow the male electrical connector element to extend through it and surround the male electrical connector element. This can provide the squib connector assembly that can adequately meet the demand for miniaturization and space saving.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 7, 2004
    Assignee: J.S.T. Mfg. Co., Ltd.
    Inventors: Akira Nagamine, Takashi Iida
  • Patent number: 6699059
    Abstract: An electrical connector assembly of the present invention includes a first component for supporting a first electrical connector element; a second component for supporting a second electrical connector element inserted in the first electrical connector element to be fitted therein; a short-circuit element, fitted in the first component, for electrically short-circuit the first electrical connector element; and a locking element engageable with the second component in a locked manner. The locking element is so structured that when the second component is inserted in the first component to be fitted therein, the locking element can make the short-circuit element move back to its non-short-circuit position and also can move to engage with the first component. The engagement of the locking element with the first component allows the first component and the second component to be locked against disconnection.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: March 2, 2004
    Assignee: J.S.T. Mfg., Co., Ltd.
    Inventors: Akira Nagamine, Takashi Iida
  • Publication number: 20030076361
    Abstract: In an image stitcher for arranging a plurality of images to be stitched in m rows and n columns (both m and n are natural numbers) on a monitor screen such that their respective arrangement positions conform to an actual relative positional relationship, to stitch all the images utilizing information related to the arrangement position of each of the images, the image stitcher comprises means for displaying on the monitor screen an image arrangement pattern selection screen including a plurality of types of image arrangement patterns for arranging the plurality of images to be stitched in m rows and n columns on the monitor screen, means for causing a user to select one of the plurality of types of image arrangement patterns on the image arrangement pattern selection screen, and means for arranging the plurality of images to be stitched in m rows and n columns on the monitor screen in accordance with the image arrangement pattern selected by the user.
    Type: Application
    Filed: September 10, 2002
    Publication date: April 24, 2003
    Inventors: Haruo Hatanaka, Takashi Iida, Naoki Chiba
  • Patent number: 6544060
    Abstract: The present invention aims to prevent forcing of pins when a female connector is obliquely inserted into a shunt. A shunt fits into a cylindrical socket concavely formed in an external face of a housing of an airbag inflator and short-circuits of a pair of contact pins of a squib of the inflator. These pins rise at the center of the socket from the bottom to a point near to the opening. The shunt includes an annular wall having a fitting hole into which the pins enter from the bottom side of the center thereof and into which a female connector fits from the top side, and a short-circuit piece provided on the annular wall, which will contact both of the pins when the shunt is fitted into the socket, and will be pushed to move away from the pins when the female connector is fitted into the fitting hole.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: April 8, 2003
    Assignees: Toyota Jidosha Kabushiki Kaisha, J.S.T. Mfg. Co., Ltd.
    Inventors: Masanori Wakui, Atsushi Nishida, Akira Nagamine, Takashi Iida
  • Publication number: 20020160645
    Abstract: An electrical connector assembly of the present invention includes a first component for supporting a first electrical connector element; a second component for supporting a second electrical connector element inserted in the first electrical connector element to be fitted therein; a short-circuit element, fitted in the first component, for electrically short-circuit the first electrical connector element; and a locking element engageable with the second component in a locked manner. The locking element is so structured that when the second component is inserted in the first component to be fitted therein, the locking element can make the short-circuit element move back to its non-short-circuit position and also can move to engage with the first component. The engagement of the locking element with the first component allows the first component and the second component to be locked against disconnection.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagamine, Takashi Iida
  • Publication number: 20020154494
    Abstract: A squib connector assembly for energizing a gas producer to make it ignite, the squib connector assembly comprising a first component for supporting a male electrical connector element; a second component for supporting a female electrical connector element engageable with the male electrical connector element; and a short-circuit element selectively switchable between a short-circuit position to electrically short-circuit the male electrical connector element and a non-short-circuit position. A flat-plate-like noise filter having electromagnetic wave absorbing material is arranged between the first component and the short-circuit element, so as to allow the male electrical connector element to extend through it and surround the male electrical connector element. This can provide the squib connector assembly that can adequately meet the demand for miniaturization and space saving.
    Type: Application
    Filed: March 20, 2002
    Publication date: October 24, 2002
    Inventors: Akira Nagamine, Takashi Iida
  • Publication number: 20020025708
    Abstract: The present invention aims to prevent forcing of pins when a female connector is obliquely inserted into a shunt.
    Type: Application
    Filed: August 31, 2001
    Publication date: February 28, 2002
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masanori Wakui, Atsushi Nishida, Akira Nagamine, Takashi Iida
  • Patent number: 6350145
    Abstract: An FPC crimp terminal comprising a bottom plate being formed from a flat plate and a fixing part rising from an edge of the bottom plate, said FPC crimp terminal being formed in such a way that when a core or a lead wire is brought into direct contact with a conductor of an FPC, the fixing part is made to pierce the FPC from its back or front and the top end of the fixing part coming out of the FPC is bent towards the bottom plate, the core or the lead wire and the FPC will be pinched between the top end of the fixing part and the bottom plate. As the fixing part is used to effect the piercing process and the connecting process at the same time, the FPC crimp terminal can be compactified and the work efficiency can be enhanced through reduction in the number of processes.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: February 26, 2002
    Assignee: Japan Solderless Terminal Mfg. Co., Ltd.
    Inventors: Ping Chen, Takashi Iida
  • Patent number: 6013924
    Abstract: A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: January 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Toru Osajima, Noboru Yokota, Takashi Iida, Masashi Takase, Shigenori Ichinose
  • Patent number: 6002429
    Abstract: An image sensing device that provides image data to an external device adjusts the resolution at which the image is sensed in accordance with format requirements of the external device. The format requirements of the external device can be automatically detected, or entered by a user. The operating parameters of a line sensor, to scan the image in a subscanning direction, are varied in accordance with the format requirements. These operating parameters can be the integration cycle of the sensor, and/or the speed at which the image is optically scanned past the sensor.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: December 14, 1999
    Assignee: Minolta Co., Ltd.
    Inventors: Keizou Ochi, Takashi Iida, Hideyuki Kanbayashi, Takashi Kondo
  • Patent number: 5672895
    Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: September 30, 1997
    Assignee: Fujitsu, Ltd.
    Inventors: Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Akinori Tahara, Isao Amano, Tetsuya Nakajima
  • Patent number: 5500542
    Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: March 19, 1996
    Assignee: Fujitsu Limited
    Inventors: Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Akinori Tahara, Isao Amano, Tetsuya Nakajima
  • Patent number: 5364533
    Abstract: A process for separating and recovering serum and plasma components from a whole blood sample including passing a whole blood sample through a separating filter formed of a blood cell separating layer composed mainly of fibers impregnated with a coating agent. A device includes a blood collector having a needle at one end and a blood suction means at the other end, and a separating filter including a blood cell separating layer, the filter being provided in the intermediate zone of the blood collector, whereby a whole blood sample sucked through the needle by depressurizing the blood suction means is passed through the separating filter.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: November 15, 1994
    Assignee: Sanwa Kagaku Kenkyusho Co., Ltd.
    Inventors: Shinji Ogura, Hiroshi Okada, Shizuo Uno, Takashi Iida, Hiromoto Asai, Masayasu Kurono, Kiichi Sawai
  • Patent number: 5258798
    Abstract: A camera has a zoom lens which includes a variator and a compensator. However, in order to simplify the whole external form of the camera, reduce the size thereof, and further to materially eliminate the treatment of appearance of the taking lens, a linear movement means which includes a threaded shaft provided for linearlly moving a variator and a compensator composing a zoom lens and the nuts to be engaged with the threaded shaft and an electrically driving means for driving this linear movement means are covered by a housing of a camera body, a zoom operation key provided on this housing is caused to be operationally related to an electric circuit which drives and controls the motor.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: November 2, 1993
    Assignee: Minolta Camera Kabushiki Kaisha
    Inventors: Takashi Iida, Hiroyuki Tsumazawa, Masatoshi Itoh, Hiroshi Kiten
  • Patent number: 5227638
    Abstract: Photoluminescence or electroluminescence from a material substrate is measured in a photon-counting range. Luminous efficiency of the substrate in its normal operation range is evaluated on the basis of the measured data. The luminescence is measured in an excitation range of the material including a transition excitation level corresponding to a transition luminous level from a low luminous range to a regular, intense luminous range. Two-dimensional distribution of the luminous efficiencies can be obtained by measuring the luminescence from small divided areas of the substrate.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: July 13, 1993
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yoshihiko Mizushima, Takashi Iida, Eiji Inuzuka
  • Patent number: 5109358
    Abstract: An optical flip-flop circuit which includes an electrical power source for providing an electrical signal, a light-receiving element provided in series with the power source for switching the electrical signal in response to an optical signal, a light-emitting element for emitting the optical signal in response to the electric signal, an electrical signal path between the light-receiving element and the light-emitting element, whereby the electrical signal passes from the power source to the light-emitting element in response to the optical signal received by the light-receiving element, a light path for directing the optical signal from the light-emitting element to the light-receiving element, wherein the light path and the electrical signal path form a signal loop through which a signal circulates, said circulating signal comprising the electrical signal through the electrical signal path portion of the signal loop and the optical signal through the light path portion of the signal loop, and input/output m
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: April 28, 1992
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Yoshihiko Mizushima, Kazutoshi Nakajima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Kenichi Sugimoto, Hirofumi Kan
  • Patent number: 5068815
    Abstract: SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: November 26, 1991
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yoshihiko Mizushima, Kazutoshi Nakajima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Kenichi Sugimoto, Tomoko Suzuki, Hirofumi Kan