Abstract: The semiconductor device SD1a includes a first wiring M2 and a second wiring M3. The semiconductor device includes a first conductor pattern DM, a first via V2 in contact with the first wiring M2 and the second wiring M3, and a second via DV1,DV2,DV3,DV4 in contact with the first conductor pattern DM and the second wiring M3. In plan view, the distance between the second via DV1 closest to the corner portion CI of the second wire M3 and the corner portion CI is shorter than the distance between the first via V2 and the corner portion CI, and the distance between the second vias adjacent to each other is shorter than the distance between the second via DV3 closest to the first via V2 and the first via V2.

Abstract: The semiconductor device has a wiring M 2, an interlayer insulating film IL3 formed on the wiring M 2, and two wirings M 3 formed on the interlayer insulating film IL3, and the wiring M 3 is connected to the wiring M 2 by a conductor layer PG2 formed in the interlayer insulating film IL3. A recess CC3 is formed on the upper surface IL3a of the interlayer insulating film IL3, and the recess CC3 is defined by a side surface S 31 connected to the upper surface IL3a and a side surface S 32 connected to the side surface S 31, and the side surface S 32 is inclined so that the width WC3 of the recess CC3 decreases in the direction from the upper surface IL3a of the interlayer insulating film IL3 toward the upper surface IL2a of the interlayer insulating film IL2.

Abstract: The semiconductor device has a wiring M 2, an interlayer insulating film IL3 formed on the wiring M 2, and two wirings M 3 formed on the interlayer insulating film IL3, and the wiring M 3 is connected to the wiring M 2 by a conductor layer PG2 formed in the interlayer insulating film IL3. A recess CC3 is formed on the upper surface IL3a of the interlayer insulating film IL3, and the recess CC3 is defined by a side surface S 31 connected to the upper surface IL3a and a side surface S 32 connected to the side surface S 31, and the side surface S 32 is inclined so that the width WC3 of the recess CC3 decreases in the direction from the upper surface IL3a of the interlayer insulating film IL3 toward the upper surface IL2a of the interlayer insulating film IL2.

Abstract: The semiconductor device SD1a includes a first wiring M2 and a second wiring M3. The semiconductor device includes a first conductor pattern DM, a first via V2 in contact with the first wiring M2 and the second wiring M3, and a second via DV1, DV2, DV3, DV4 in contact with the first conductor pattern DM and the second wiring M3. In plan view, the distance between the second via DV1 closest to the corner portion CI of the second wire M3 and the corner portion CI is shorter than the distance between the first via V2 and the corner portion CI, and the distance between the second vias adjacent to each other is shorter than the distance between the second via DV3 closest to the first via V2 and the first via V2.

Abstract: The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.

Abstract: The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer. In addition, the first insulating film is formed on one side of the active region from the surface of SOI layer to the buried insulating film. In addition, the second insulating film is formed on the other side of the active region from the surface of SOI layer to a predetermined depth that does not reach the buried insulating film. In addition, the contact portion is provided toward the side where the first insulating film exists, off the center of the active region in a plan view.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant.

Abstract: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film is not etched. Next, an N-type impurity is implanted through the oxide film to form source/drain regions in an upper portion of the SOI layer. In this step, adjusting the implantation energy so that the impurity reaches the buried oxide film provides the source/drain regions in contact with the buried oxide film.

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: Formed on an insulator are an N? type semiconductor layer having a partial isolator formed on its surface and a P? type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain being N+ type semiconductor layers are provided on the semiconductor layer to form an NMOS transistor. A pn junction formed by the semiconductor layers is provided in a CMOS transistor made up of the transistors. The pn junction is positioned separately from the partial isolators where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction.