Patents by Inventor Takashi Ipposhi
Takashi Ipposhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7494880Abstract: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film is not etched. Next, an N-type impurity is implanted through the oxide film to form source/drain regions in an upper portion of the SOI layer In this step, adjusting the implantation energy so that the impurity reaches the buried oxide film provides the source/drain regions in contact with the buried oxide film.Type: GrantFiled: October 3, 2005Date of Patent: February 24, 2009Assignee: Renesas Technology Corp.Inventor: Takashi Ipposhi
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Patent number: 7494883Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.Type: GrantFiled: October 5, 2006Date of Patent: February 24, 2009Assignee: Renesas Technology Corp.Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda
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Publication number: 20090047757Abstract: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.Type: ApplicationFiled: October 17, 2008Publication date: February 19, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Mikio TSUJIUCHI, Toshiaki IWAMATSU, Takashi IPPOSHI
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Patent number: 7470582Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.Type: GrantFiled: October 18, 2007Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
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Publication number: 20080315313Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.Type: ApplicationFiled: October 3, 2007Publication date: December 25, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuo YAMAGUCHI, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
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Patent number: 7453135Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.Type: GrantFiled: December 29, 2006Date of Patent: November 18, 2008Assignee: Renesas Technology Corp.Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
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Patent number: 7449749Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).Type: GrantFiled: June 8, 2006Date of Patent: November 11, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
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Publication number: 20080261387Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.Type: ApplicationFiled: June 23, 2008Publication date: October 23, 2008Applicant: Renesas Technology Corp.Inventors: Takashi IPPOSHI, Toshiaki Iwamatsu, Shigeto Maegawa
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Publication number: 20080211035Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.Type: ApplicationFiled: August 15, 2007Publication date: September 4, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yuuichi Hirano, Takashi Ipposhi, Shigeto Maegawa, Koji Nii
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Publication number: 20080203479Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.Type: ApplicationFiled: April 23, 2008Publication date: August 28, 2008Applicant: Renesas Technology Corp.Inventors: Tetsuya WATANABE, Takashi IPPOSHI
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Publication number: 20080179676Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.Type: ApplicationFiled: January 9, 2008Publication date: July 31, 2008Inventors: Yuichi HIRANO, Takashi Ipposhi, Toshiaki Iwamatsu, Yukio Maki, Mikio Tsujiuchi
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Patent number: 7402865Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.Type: GrantFiled: August 25, 2005Date of Patent: July 22, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Shigeto Maegawa
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Patent number: 7391095Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.Type: GrantFiled: November 2, 2006Date of Patent: June 24, 2008Assignee: Renesas Technology Corp.Inventors: Tetsuya Watanabe, Takashi Ipposhi
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Publication number: 20080128810Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: December 21, 2007Publication date: June 5, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
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Publication number: 20080128814Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: December 21, 2007Publication date: June 5, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
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Patent number: 7382026Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.Type: GrantFiled: August 15, 2007Date of Patent: June 3, 2008Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Takashi Ipposhi, Shigeto Maegawa, Koji Nii
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Patent number: 7358555Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.Type: GrantFiled: April 24, 2006Date of Patent: April 15, 2008Assignee: Renesas Technology Corp.Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Tatsuhiko Ikeda, Shigeto Maegawa
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Publication number: 20080081436Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.Type: ApplicationFiled: October 30, 2007Publication date: April 3, 2008Applicant: Renesas Technology Corp.Inventors: Shigenobu MAEDA, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
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Patent number: 7352049Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.Type: GrantFiled: August 8, 2006Date of Patent: April 1, 2008Assignee: Renesas Technology Corp.Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
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Publication number: 20080067593Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: October 31, 2007Publication date: March 20, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi