Patents by Inventor Takashi Ishida

Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11016509
    Abstract: A laser tracker is installed on the ground, and an active target is mounted on an air vehicle. A reference coordinate system is set for the laser tracker, and a flight scenario created in advance based on a 3D model is used. Flight of the air vehicle is performed while an amount of deviation from the flight scenario is being calculated using position information obtained by the laser tracker, and corrections are being made. The air vehicle is instructed not only on an amount of movement but also on speed, so that efficient flight can be performed in consideration of battery capacity.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 25, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Iwakura, Takayuki Ishida
  • Patent number: 11014092
    Abstract: An apparatus and method to efficiently recover noble metals such as gold, silver and copper and aluminum from incineration ash, and effectively use ash after recovering the noble metals and others. An incineration ash treatment apparatus 1 including: a crusher for crushing an incineration ash A1 to be less or equal to 5 mm in maximum particle diameter, or/and a classifier for classifying an incineration ash to obtain an incineration ash whose maximum particle diameter is less or equal to 5 mm; an eddy current separator 8 for separating an incineration ash whose maximum particle diameter is less or equal to 5 mm discharged from the crusher or/and the classifier into a conductor E and a nonconductor I; a specific gravity separator for separating a conductor discharged from the eddy current separator 8 into a high gravity material H2 and a low gravity material L2. The specific gravity separator can be an air table 10.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 25, 2021
    Assignee: TAIHEIYO CEMENT CORPORATION
    Inventors: Kou Takizawa, Tomonori Takemoto, Takashi Hanada, Yasuyuki Ishida
  • Patent number: 11018217
    Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Takahiro Sugimoto, Hiroshi Kanno, Tatsuya Okamoto
  • Publication number: 20210141983
    Abstract: [Object] To appropriately make apparent the feature part of the object shape. [Solving Means] This technology moves each face in a normal direction of each face from data representing an object shape of a CAD model by discretizing a surface of the CAD model into a grid and arranging faces surrounded by discrete points, to thereby generate an expansion model or a contraction model of the object shape of the CAD model, considers that the surface of the expansion model or the contraction model is uniformly charged and solves a Laplace's equation for an electrostatic field on the surface according to a boundary element method to thereby determine a potential distribution on the surface of the expansion model or the contraction model, and detects a feature part of the object shape on the basis of the determined potential distribution.
    Type: Application
    Filed: April 1, 2019
    Publication date: May 13, 2021
    Inventors: Masashi KANAMORI, Takashi ISHIDA, Atsushi HASHIMOTO, Takashi AOYAMA
  • Publication number: 20210134862
    Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each having a light receiving region, the avalanche photodiodes being arranged in a matrix at the semiconductor substrate, and a plurality of through-electrodes electrically connected to corresponding light receiving regions. The plurality of through-electrodes are arranged for each area surrounded by four mutually adjacent avalanche photodiodes of the plurality of avalanche photodiodes. Each of the light receiving regions has, when viewed from a direction perpendicular to a first principal surface of the semiconductor substrate, a polygonal shape including a pair of first sides opposing each other in a row direction and extending in a column direction and four second side opposing four through-electrodes surrounding the light receiving region and extending in directions intersecting with the row direction and the column direction. The length of the first side is shorter than the length of the second side.
    Type: Application
    Filed: July 26, 2017
    Publication date: May 6, 2021
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Atsushi ISHIDA, Terumasa NAGANO, Takashi BABA
  • Publication number: 20210111189
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
  • Publication number: 20210074592
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.
    Type: Application
    Filed: March 6, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomonari SHIODA, Takashi ISHIDA
  • Publication number: 20210039339
    Abstract: A method for molding a composite material includes a conductive wire-shaped material arrangement step and a magnetic field application step. The conductive wire-shaped material arrangement step is a step for arranging, in a pre-reaction composite material including reinforcing fibers, a plurality of conductive wire-shaped materials along a direction intersecting the reinforcing fibers with intervals wider than intervals of the reinforcing fibers in a plane on which the reinforcing fibers are arranged. The magnetic field application step is a step for applying a magnetic field in a direction intersecting the plane on which the reinforcing fibers are arranged.
    Type: Application
    Filed: January 31, 2019
    Publication date: February 11, 2021
    Inventors: Nobuyuki KAMIHARA, Kiyoka TAKAGI, Toshio ABE, Mikio MURAOKA, Toshiyuki TAKAYANAGI, Naomoto ISHIKAWA, Wataru NISHIMURA, Sota KAMO, Tomoharu DENGO, Takashi ISHIDA, Yukihiro YOSHIDA
  • Patent number: 10916562
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Publication number: 20200279864
    Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 3, 2020
    Inventors: Ken KOMIYA, Takashi ISHIDA, Hiroshi KANNO
  • Patent number: 10751046
    Abstract: A medical suture needle made of stainless steel includes a cutting blade component and a body part continuing to the cutting blade component. The cutting blade component, whose degree of thickness decreases from the body part to a sharp point, includes a first cutting blade part and a second cutting blade part continuing from the first cutting blade part. The first cutting blade part includes two first slanted surfaces formed sandwiching an apex and a first bottom surface sandwiched by the two first slanted surfaces. Cutting blades are formed at an edge constituting the apex and at edges where the first bottom surface and the two first slanted surfaces intersect. The second cutting blade part includes first slanted surfaces, second slanted surfaces having rims approximately parallel to the apex and formed on the respective first slanted surfaces, and a second bottom surface sandwiched by the second slanted surfaces.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 25, 2020
    Assignee: MANI, INC.
    Inventors: Takashi Ishida, Shinichi Akutsu, Motoichi Sugino
  • Publication number: 20200189214
    Abstract: A bladder bag is a mold for molding inside of a composite material structure. The composite material structure includes a narrow portion formed by narrowing a part of the inside and a space portion formed so as to be adjacent to the narrow portion. The bladder bag includes a bladder bag main body and a cord-like member. The bladder bag main body includes a narrow molding portion for molding the narrow portion of the composite material structure, a space molding portion for molding the space portion of the composite material structure, and an air intake for introducing air. The cord-like member is provided inside the bladder bag main body, passes through the narrow molding portion from the air intake, and is connected to an inner surface of the space molding portion.
    Type: Application
    Filed: October 13, 2017
    Publication date: June 18, 2020
    Inventors: Kiyoka TAKAGI, Jun ISHIDA, Sota KAMO, Katsuya YOSHINO, Toshio ABE, Koichi HASEGAWA, Yoshihiro SUGIYAMA, Takashi ISHIDA
  • Patent number: 10658295
    Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Kawai, Takashi Ishida, Shuichi Toriyama
  • Publication number: 20200127081
    Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 23, 2020
    Inventors: Takashi ISHIDA, Takahiro SUGIMOTO, Hiroshi KANNO, Tatsuya OKAMOTO
  • Patent number: 10591863
    Abstract: An image forming apparatus includes an apparatus body, a wall face of the apparatus body having an ejection opening from which a sheet conveyed in a first direction is ejected, a sheet support to support the sheet discharged from the discharge opening in the first direction, and a mount to mount the sheet support to the apparatus body. The mount includes an abutting portion including an abutting face that contacts a wall face of the apparatus body, and a projection projecting in a second direction opposite to the first direction from the abutting face. The abutting face extends in a vertically downward direction from the projection, and the projection is fixed to the apparatus body in a vertical direction.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Ishida, Goro Katsuyama
  • Patent number: 10575845
    Abstract: Strength of a front end part having a sharp point of a medical suture needle is maintained and resistance when piercing tissue is reduced. There is provided a medical suture needle having a triangular cross section made of austenitic stainless steel having a fibrously extending structure, having two first slanted surfaces (11) ground and sandwiching a ridge (20), and a bottom surface (13) sandwiched between the two first slanted surfaces and ground. The ridge is formed comprising a first cutting blade (1) that is formed by the two first slanted surfaces (11) intersecting, a ridge part (20) that is formed on a body part side of the first cutting blade without the first slanted surfaces (11) intersecting, and a second cutting blade (2) that is formed by two second slanted surfaces (12) ground, intersecting and sandwiching the first cutting blade (1) on a front end side of the first cutting blade (1).
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 3, 2020
    Assignee: MANI, INC.
    Inventors: Masaaki Matsutani, Shinichi Akutsu, Masato Mizui, Takashi Ishida
  • Patent number: 10562243
    Abstract: A core (20) and a bag (22, 24) are provided which are used to shape an FRP structure (10; 30). The bag (22, 24) has a core bag section (24) which covers the outer circumference of the core (20), and a coverture bag section (22) which covers a plurality of fiber components (12, 14; 12, 14, 16).
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 18, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshio Abe, Kiyoka Takagi, Takayuki Koyama, Katsuya Yoshino, Kazuaki Kishimoto, Koichi Saito, Takashi Ishida
  • Publication number: 20190355742
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: November 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki Fukuzumi, Yuki Sugiura, Shinya Arai, Fumie Kikushima, Keisuke Suda, Takashi Ishida
  • Publication number: 20190295956
    Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tomoya Kawai, Takashi Ishida, Shuichi Toriyama
  • Publication number: 20190267398
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI