Patents by Inventor Takashi Ishida

Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374043
    Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each having a light receiving region, the avalanche photodiodes being arranged in a matrix at the semiconductor substrate, and a plurality of through-electrodes electrically connected to corresponding light receiving regions. The plurality of through-electrodes are arranged for each area surrounded by four mutually adjacent avalanche photodiodes of the plurality of avalanche photodiodes. Each of the light receiving regions has, when viewed from a direction perpendicular to a first principal surface of the semiconductor substrate, a polygonal shape including a pair of first sides opposing each other in a row direction and extending in a column direction and four second side opposing four through-electrodes surrounding the light receiving region and extending in directions intersecting with the row direction and the column direction. The length of the first side is shorter than the length of the second side.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 28, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Atsushi Ishida, Terumasa Nagano, Takashi Baba
  • Patent number: 11362127
    Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each including a light receiving region disposed at a first principal surface side of the semiconductor substrate, the avalanche photodiodes being arranged two-dimensionally at the semiconductor substrate, and a through-electrode electrically connected to a corresponding light receiving region. The through-electrode is provided in a through-hole penetrating through the semiconductor substrate in an area where the plurality of avalanche photodiodes are arranged two-dimensionally. At the first principal surface side of the semiconductor substrate, a groove surrounding the through-hole is formed between the through-hole and the light receiving region adjacent to the through-hole.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 14, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Atsushi Ishida, Noburo Hosokawa, Terumasa Nagano, Takashi Baba
  • Publication number: 20220115403
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
  • Publication number: 20220080682
    Abstract: A method for forming a composite material including reinforcing fibers includes connecting end portions of the reinforcing fibers with equipotential materials to form an electroconductive loop including the reinforcing fibers in the composite material before reaction; and applying a magnetic field in a direction intersecting a plane formed by the electroconductive loop.
    Type: Application
    Filed: January 16, 2020
    Publication date: March 17, 2022
    Inventors: Toshiyuki TAKAYANAGI, Naomoto ISHIKAWA, Wataru NISHIMURA, Nobuyuki KAMIHARA, Sota KAMO, Kiyoka TAKAGI, Takashi ISHIDA, Tomoharu DENGO, Mikio MURAOKA, Yukihiro YOSHIDA
  • Publication number: 20220048857
    Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.
    Type: Application
    Filed: September 10, 2021
    Publication date: February 17, 2022
    Applicants: NATIONAL UNIVERSITY CORPORATION KUMAMOTO UNIVERSITY, Nippon Soda Co., Ltd.
    Inventors: Hayato ISHIKAWA, Tokio TANI, Shinichiro SAWA, Takashi ISHIDA, Yusuke FUKUSHIMA, Jun INAGAKI
  • Patent number: 11251193
    Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 15, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ken Komiya, Takashi Ishida, Hiroshi Kanno
  • Publication number: 20220015996
    Abstract: A water-type or oil-in-water type cosmetic provided with a watery feeling in use and high ultraviolet protection ability. The water-type or oil-in-water-type cosmetic according to the present invention is characterized by containing (A) a porous spherical powder having an average particle size of 1 to 4 ?m and an oil absorption rate of 160 ml/100 g or lower; and (B) an ultraviolet absorption agent.
    Type: Application
    Filed: November 18, 2019
    Publication date: January 20, 2022
    Applicant: Shiseido Company, Ltd.
    Inventors: Yurika WATANABE, Takashi ISHIDA, Kazuhiro YAMAGUCHI
  • Publication number: 20210391011
    Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.
    Type: Application
    Filed: March 3, 2021
    Publication date: December 16, 2021
    Inventors: Takashi ISHIDA, Hiroshi KANNO
  • Patent number: 11142497
    Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 12, 2021
    Assignees: National University Corporation Kumamoto University, Nippon Soda Co., Ltd.
    Inventors: Hayato Ishikawa, Tokio Tani, Shinichiro Sawa, Takashi Ishida, Yusuke Fukushima, Jun Inagaki
  • Publication number: 20210284434
    Abstract: An extraction bag 1A includes a bag main body 3 formed of a water permeable filter sheet 2, a thin plate-like member 10 provided on an outer surface of the bag main body 3, and an extraction material filled in the bag main body 3. The bag main body 3 has a first surface 3A and a second surface 3B opposed to each other, and an upper side 4a corresponding to edges thereof. The thin plate-like member 10 includes a first member 10A on the first surface 3A of the bag main body, and a second member 10B on the second surface 3B of the bag main body, and these 10A and 10B are continuous with each other via a first horizontal folding line Lh1 extending along the upper side 4a.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 16, 2021
    Applicant: OHKI Co., Ltd.
    Inventors: Takashi ISHIDA, Mitsunori SAITOH
  • Publication number: 20210276950
    Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.
    Type: Application
    Filed: February 6, 2018
    Publication date: September 9, 2021
    Applicants: NATIONAL UNIVERSITY CORPORATION KUMAMOTO UNIVERSITY, Nippon Soda Co., Ltd.
    Inventors: Hayato ISHIKAWA, Tokio TANI, Shinichiro SAWA, Takashi ISHIDA, Yusuke FUKUSHIMA, Jun INAGAKI
  • Publication number: 20210273055
    Abstract: A semiconductor storage device according to the present embodiment includes a first semiconductor layer containing impurities. A stacked body is provided above the first semiconductor layer and includes insulating layers and conductive layers that are alternately stacked. A semiconductor body penetrates through the stacked body in a stacking direction to reach the first semiconductor layer and includes a lower region on a side of the first semiconductor layer and an upper region positioned above the lower region. A charge accumulation part is provided between the semiconductor bodies and the conductive layers. An impurity concentration of the lower region of the semiconductor body is higher than that of the first semiconductor layer.
    Type: Application
    Filed: September 14, 2020
    Publication date: September 2, 2021
    Inventors: Naomi YANAI, Yasuhito YOSHIMIZU, Takashi ISHIDA
  • Patent number: 11075122
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 27, 2021
    Assignee: Kioxia Corporation
    Inventors: Tomonari Shioda, Takashi Ishida
  • Patent number: 11065832
    Abstract: A bladder bag is a mold for molding inside of a composite material structure. The composite material structure includes a narrow portion formed by narrowing a part of the inside and a space portion formed so as to be adjacent to the narrow portion. The bladder bag includes a bladder bag main body and a cord-like member. The bladder bag main body includes a narrow molding portion for molding the narrow portion of the composite material structure, a space molding portion for molding the space portion of the composite material structure, and an air intake for introducing air. The cord-like member is provided inside the bladder bag main body, passes through the narrow molding portion from the air intake, and is connected to an inner surface of the space molding portion.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 20, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Kiyoka Takagi, Jun Ishida, Sota Kamo, Katsuya Yoshino, Toshio Abe, Koichi Hasegawa, Yoshihiro Sugiyama, Takashi Ishida
  • Patent number: 11018217
    Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Takahiro Sugimoto, Hiroshi Kanno, Tatsuya Okamoto
  • Publication number: 20210141983
    Abstract: [Object] To appropriately make apparent the feature part of the object shape. [Solving Means] This technology moves each face in a normal direction of each face from data representing an object shape of a CAD model by discretizing a surface of the CAD model into a grid and arranging faces surrounded by discrete points, to thereby generate an expansion model or a contraction model of the object shape of the CAD model, considers that the surface of the expansion model or the contraction model is uniformly charged and solves a Laplace's equation for an electrostatic field on the surface according to a boundary element method to thereby determine a potential distribution on the surface of the expansion model or the contraction model, and detects a feature part of the object shape on the basis of the determined potential distribution.
    Type: Application
    Filed: April 1, 2019
    Publication date: May 13, 2021
    Inventors: Masashi KANAMORI, Takashi ISHIDA, Atsushi HASHIMOTO, Takashi AOYAMA
  • Publication number: 20210111189
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
  • Publication number: 20210074592
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.
    Type: Application
    Filed: March 6, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomonari SHIODA, Takashi ISHIDA
  • Publication number: 20210039339
    Abstract: A method for molding a composite material includes a conductive wire-shaped material arrangement step and a magnetic field application step. The conductive wire-shaped material arrangement step is a step for arranging, in a pre-reaction composite material including reinforcing fibers, a plurality of conductive wire-shaped materials along a direction intersecting the reinforcing fibers with intervals wider than intervals of the reinforcing fibers in a plane on which the reinforcing fibers are arranged. The magnetic field application step is a step for applying a magnetic field in a direction intersecting the plane on which the reinforcing fibers are arranged.
    Type: Application
    Filed: January 31, 2019
    Publication date: February 11, 2021
    Inventors: Nobuyuki KAMIHARA, Kiyoka TAKAGI, Toshio ABE, Mikio MURAOKA, Toshiyuki TAKAYANAGI, Naomoto ISHIKAWA, Wataru NISHIMURA, Sota KAMO, Tomoharu DENGO, Takashi ISHIDA, Yukihiro YOSHIDA
  • Patent number: 10916562
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji