Patents by Inventor Takashi Ishida
Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250104838Abstract: In an activity support device, a plan acquisition means acquires a target physical activity amount of a user in a predetermined period and a predictive physical activity amount representing an expected expenditure of a physical activity amount. An expended physical activity amount acquisition means acquires an expended physical activity amount of the user up to a current time in the predetermined period. A total expended physical activity amount acquisition means derives a total expended physical activity amount of the user in the predetermined period, based on the predictive physical activity amount and the expended physical amount. An activity determination means determines a physical activity to the user from among physical activity options by comparing the target physical amount and the total expended physical amount. Accordingly, it is possible for the activity support device to support a user in making a decision regarding the physical activity.Type: ApplicationFiled: September 26, 2024Publication date: March 27, 2025Applicant: NEC CorporationInventors: Tatsunori NAGASAWA, Masaru Yanai, Seishi Handa, Tomonori Ishida, Makoto Iwasaki, Noriaki Kobayashi, Takashi Kojima, Naoko Kurisaki, Hideki Muramatsu, Motoharu Ohtake, Nanami Sakurai, Yasuyuki Taguchi, Takayuki Takimoto, Noritsugu Yamanaka, Kosei Kobayashi
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Patent number: 12261048Abstract: A method for manufacturing a semiconductor device includes: irradiating, with laser light, a semiconductor substrate having a p-type first semiconductor layer and an n-type second semiconductor layer so that the laser light converges on an interface between the first semiconductor layer and the second semiconductor layer, wherein each of the p-type first semiconductor layer and the n-type second semiconductor layer placed on the first semiconductor layer is formed of a compound semiconductor; and separating the semiconductor substrate into the first semiconductor layer and the second semiconductor layer along the interface.Type: GrantFiled: October 25, 2022Date of Patent: March 25, 2025Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies CorporationInventor: Takashi Ishida
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Patent number: 12255604Abstract: An acoustic wave device includes a piezoelectric layer, the piezoelectric layer being a rotated Y-cut lithium niobate substrate or an X-cut lithium tantalate substrate; an upper conductive layer having a substantially consistent density, on or over the upper surface of the piezoelectric layer; a lower conductive layer having a substantially consistent density, on or below the lower surface of the piezoelectric layer; and a first additional film having a substantially consistent density, wherein at least one of the upper and lower conductive layers is mainly made of ruthenium, chrome, copper, molybdenum, tungsten, tantalum, platinum, rhodium, or iridium, and wherein at least a part of the first additional film is in the resonance region in the plan view, and the density of the first additional film is equal to or less than the density of aluminum.Type: GrantFiled: March 11, 2021Date of Patent: March 18, 2025Assignee: TAIYO YUDEN CO., LTD.Inventors: Mamoru Ishida, Takashi Matsuda
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Patent number: 12239643Abstract: A therapeutic agent for treating at least one disease selected from the group consisting of inflammatory diseases, autoimmune diseases, fibrotic diseases, and cancer diseases, comprising: at least one selected from the group consisting of a compound represented by the following general formula (1) and pharmacologically acceptable salts thereof as an active ingredient. [In the formula (1), R1 and R2 may be the same or different and each represents a hydrogen atom, a halogen atom, a hydroxyl group, a carboxy group, a cyano group, an optionally substituted C1-6 alkyl group et al.; R3 represents a hydrogen atom; R4 represents an optionally substituted 4- to 10-membered monocyclic heterocyclic group containing 1 to 4 heteroatoms selected from an oxygen atom, a nitrogen atom, and a sulfur atom; X represents a group represented by the following formula: —CH2—, —CH2—CH2—, —CH2—CH2—CH2—, or —CH2—O—CH2—; and Z represents a hydrogen atom or a hydroxyl group.Type: GrantFiled: June 27, 2019Date of Patent: March 4, 2025Assignee: MEIJI SEIKA PHARMA CO., LTD.Inventors: Natsuki Ishida, Yuji Tabata, Takashi Matsuhira, Keiji Tamura, Takeru Yamakawa, Satoshi Isshiki, Yoshinari Wakiyama, Shohei Ouchi
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Patent number: 12218170Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each including a light receiving region disposed at a first principal surface side of the semiconductor substrate, the avalanche photodiodes being arranged two-dimensionally at the semiconductor substrate, and a through-electrode electrically connected to a corresponding light receiving region. The through-electrode is provided in a through-hole penetrating through the semiconductor substrate in an area where the plurality of avalanche photodiodes are arranged two-dimensionally. At the first principal surface side of the semiconductor substrate, a groove surrounding the through-hole is formed between the through-hole and the light receiving region adjacent to the through-hole.Type: GrantFiled: April 6, 2022Date of Patent: February 4, 2025Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Atsushi Ishida, Noburo Hosokawa, Terumasa Nagano, Takashi Baba
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Publication number: 20240272589Abstract: A time-to-digital converter circuit that measures a time difference between a first input signal and a second input signal includes: a jitter superimposition circuit that superimposes a jitter, which changes temporally, on one of the first input signal and the second input signal to generate a first intermediate signal and a second intermediate signal; a time-to-digital converter that measures a time difference between the first intermediate signal and the second intermediate signal each time the jitter changes; and a statistical processor that statistically processes a plurality of time differences measured by the time-to-digital converter in response to a plurality of jitters, and calculates a time difference between the first input signal and the second input signal.Type: ApplicationFiled: February 1, 2024Publication date: August 15, 2024Inventors: Keno SATO, Tamotsu ICHIKAWA, Takashi ISHIDA, Toshiyuki OKAMOTO, Takayuki NAKATANI, Haruo KOBAYASHI
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Publication number: 20240251559Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Applicant: Kioxia CorporationInventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
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Patent number: 11987013Abstract: A method for forming a composite material including reinforcing fibers includes connecting end portions of the reinforcing fibers with equipotential materials to form an electroconductive loop including the reinforcing fibers in the composite material before reaction; and applying a magnetic field in a direction intersecting a plane formed by the electroconductive loop.Type: GrantFiled: January 16, 2020Date of Patent: May 21, 2024Assignees: MITSUBISHI HEAVY INDUSTRIES, LTD., AKITA UNIVERSITYInventors: Toshiyuki Takayanagi, Naomoto Ishikawa, Wataru Nishimura, Nobuyuki Kamihara, Sota Kamo, Kiyoka Takagi, Takashi Ishida, Tomoharu Dengo, Mikio Muraoka, Yukihiro Yoshida
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Patent number: 11980031Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
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Publication number: 20240014272Abstract: A semiconductor device includes a gallium nitride substrate and a pattern film disposed on a front surface of the gallium nitride substrate. In the gallium nitride substrate, a Young's modulus in a first direction along the front surface is larger than a Young's modulus in a second direction along the front surface and orthogonal to the first direction. A first ratio R1 obtained by dividing a dimension of the gallium nitride substrate in the first direction by a dimension of the gallium nitride substrate in the second direction and a second ratio R2 obtained by dividing a dimension of the pattern film in the first direction by a dimension of the pattern film in the second direction satisfy a relationship of R1<R2.Type: ApplicationFiled: July 3, 2023Publication date: January 11, 2024Inventors: Seiya HASEGAWA, Takashi USHIJIMA, Takashi ISHIDA, Shoichi ONDA, Chiaki SASAOKA, Jun KOJIMA
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Patent number: 11685716Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.Type: GrantFiled: September 10, 2021Date of Patent: June 27, 2023Assignees: National University Corporation Kumamoto University, Nippon Soda Co., Utd.Inventors: Hayato Ishikawa, Tokio Tani, Shinichiro Sawa, Takashi Ishida, Yusuke Fukushima, Jun Inagaki
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Publication number: 20230160104Abstract: A method for manufacturing a semiconductor device includes: preparing a processed wafer having a gallium nitride (GaN) wafer and an epitaxial layer on the GaN wafer; forming a device constituent part in a portion of the processes wafer adjacent to a front surface provided by the epitaxial layer; forming a modified layer inside of the processed wafer by applying a laser beam from a back surface side opposite to the front surface side: and dividing the processed wafer at the modified layer. The processed wafer prepared includes a reflective layer for reflecting the laser beam at a position separated from a planned formation position, where the modified layer is to be formed, by a predetermined distance toward the front surface side. The reflective layer contains a layer having a refractive index different from that of a GaN single crystal of an epitaxial layer.Type: ApplicationFiled: November 16, 2022Publication date: May 25, 2023Inventors: Junji OHARA, Takashi ISHIDA, Yoshitaka NAGASATO, Daisuke KAWAGUCHI, Chiaki SASAOKA, Shoichi ONDA, Jun KOJIMA
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Publication number: 20230154756Abstract: A method for manufacturing a semiconductor device includes: irradiating, with laser light, a semiconductor substrate having a p-type first semiconductor layer and an n-type second semiconductor layer so that the laser light converges on an interface between the first semiconductor layer and the second semiconductor layer, wherein each of the p-type first semiconductor layer and the n-type second semiconductor layer placed on the first semiconductor layer is formed of a compound semiconductor; and separating the semiconductor substrate into the first semiconductor layer and the second semiconductor layer along the interface.Type: ApplicationFiled: October 25, 2022Publication date: May 18, 2023Inventor: TAKASHI ISHIDA
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Patent number: 11643270Abstract: An extraction bag 1A includes a bag main body 3 formed of a water permeable filter sheet 2, a thin plate-like member 10 provided on an outer surface of the bag main body 3, and an extraction material filled in the bag main body 3. The bag main body 3 has a first surface 3A and a second surface 3B opposed to each other, and an upper side 4a corresponding to edges thereof. The thin plate-like member 10 includes a first member 10A on the first surface 3A of the bag main body, and a second member 10B on the second surface 3B of the bag main body, and these 10A and 10B are continuous with each other via a first horizontal folding line Lh1 extending along the upper side 4a.Type: GrantFiled: March 11, 2020Date of Patent: May 9, 2023Assignee: OHKI CO., LTD.Inventors: Takashi Ishida, Mitsunori Saitoh
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Publication number: 20230066475Abstract: A semiconductor storage device includes: a first stack having a first insulation film and a first conductive film alternately stacked in a first direction; a plurality of first column portions respectively including a first semiconductor portion extending in the first stack in the first direction and a charge trapping film provided on an outer circumferential surface of the first semiconductor portion; and a first isolation portion penetrating through an upper-layer portion of the first stack in the first direction, extending in a second direction that crosses the first direction, including a second insulation film and a third insulation film arranged via the second insulation film, and configured to electrically isolate the first conductive film included in the upper-layer portion of the first stack in a third direction that crosses the first and second directions.Type: ApplicationFiled: December 13, 2021Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Shun SHIMIZU, Takashi ISHIDA
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Patent number: 11574681Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.Type: GrantFiled: March 3, 2021Date of Patent: February 7, 2023Assignee: KIOXIA CORPORATIONInventors: Takashi Ishida, Hiroshi Kanno
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Publication number: 20220115403Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
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Publication number: 20220080682Abstract: A method for forming a composite material including reinforcing fibers includes connecting end portions of the reinforcing fibers with equipotential materials to form an electroconductive loop including the reinforcing fibers in the composite material before reaction; and applying a magnetic field in a direction intersecting a plane formed by the electroconductive loop.Type: ApplicationFiled: January 16, 2020Publication date: March 17, 2022Inventors: Toshiyuki TAKAYANAGI, Naomoto ISHIKAWA, Wataru NISHIMURA, Nobuyuki KAMIHARA, Sota KAMO, Kiyoka TAKAGI, Takashi ISHIDA, Tomoharu DENGO, Mikio MURAOKA, Yukihiro YOSHIDA
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Publication number: 20220048857Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.Type: ApplicationFiled: September 10, 2021Publication date: February 17, 2022Applicants: NATIONAL UNIVERSITY CORPORATION KUMAMOTO UNIVERSITY, Nippon Soda Co., Ltd.Inventors: Hayato ISHIKAWA, Tokio TANI, Shinichiro SAWA, Takashi ISHIDA, Yusuke FUKUSHIMA, Jun INAGAKI
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Patent number: 11251193Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.Type: GrantFiled: September 3, 2019Date of Patent: February 15, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ken Komiya, Takashi Ishida, Hiroshi Kanno