Patents by Inventor Takashi Ishida
Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180018755Abstract: An image processing apparatus includes circuitry that converts user voices that are input into a string of characters reflecting a statement made with the user voices, retrieves one or more items of information related to the string, stores the information being retrieved associated with identification information indicating a retrieval time when the information is retrieved, draws a graphical image including the information being stored on a projection target image to be projected by a projector, and controls the projector to project the projection target image including the graphical image, the graphical image having a size that is determined in accordance with the identification information associated with the information included in the graphical image being projected.Type: ApplicationFiled: July 6, 2017Publication date: January 18, 2018Inventors: Ryotaro FUJIYAMA, Takashi ISHIDA, Naoto TSURUOKA, Kyoko HASHIMOTO, Shin YAMAUCHI
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Publication number: 20170271356Abstract: According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.Type: ApplicationFiled: August 16, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Takashi ISHIDA
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Publication number: 20170266874Abstract: This structure is provided with a first composite material 11, a second composite material 12 joined to the first composite material 11 by a film adhesive 21 provided between the first composite material 11 and the second composite material 12, and a corner fillet part 13 provided on a corner part 15 formed by the first composite material 11 and the second composite material 12. The shape of the corner fillet part 13 is a design shape P designed in advance, and the corner fillet part 13 is formed by curing the film adhesive 21 after arranging the film adhesive 21 on the corner part 15 so as to fit into the design shape P.Type: ApplicationFiled: October 7, 2015Publication date: September 21, 2017Inventors: Toshio ABE, Kiyoka TAKAGI, Takayuki KOYAMA, Kazuaki KISHIMOTO, Koichi SAITO, Takashi ISHIDA
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Publication number: 20170263636Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.Type: ApplicationFiled: September 15, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takashi ISHIDA, Jun FUJIKI, Shinya ARAI, Fumitaka ARAI, Hideaki AOCHI, Kotaro FUJII
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Patent number: 9761606Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.Type: GrantFiled: September 15, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Ishida, Jun Fujiki, Shinya Arai, Fumitaka Arai, Hideaki Aochi, Kotaro Fujii
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Publication number: 20170252037Abstract: Strength of a front end part having a sharp point of a medical suture needle is maintained and resistance when piercing tissue is reduced. There is provided a medical suture needle having a triangular cross section made of austenitic stainless steel having a fibrously extending structure, having two first slanted surfaces (11) ground and sandwiching a ridge (20), and a bottom surface (13) sandwiched between the two first slanted surfaces and ground. The ridge is formed comprising a first cutting blade (1) that is formed by the two first slanted surfaces (11) intersecting, a ridge part (20) that is formed on a body part side of the first cutting blade without the first slanted surfaces (11) intersecting, and a second cutting blade (2) that is formed by two second slanted surfaces (12) ground, intersecting and sandwiching the first cutting blade (1) on a front end side of the first cutting blade (1).Type: ApplicationFiled: August 26, 2015Publication date: September 7, 2017Applicant: Mani, Inc.Inventors: Masaaki Matsutani, Shinichi Akutsu, Masato Mizui, Takashi Ishida
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Publication number: 20170104001Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
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Patent number: 9583505Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: GrantFiled: September 11, 2014Date of Patent: February 28, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
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Publication number: 20170043980Abstract: A sill for an elevator, wherein a first support member and a first surface member are configured as separate members, and a second support member and a second surface member are configured as separate members. One of the first and second surface members has one upper plate section forming one upper surface of the sill, a bottom plate section forming a bottom surface of a sill groove, and one side plate section forming one side surface of the sill groove. The other of the first and second surface members has another upper plate section forming another upper surface of the sill, and another side plate section forming another side surface of the sill groove. A space into which a detachment prevention member provided on a lower part of the door panel is inserted is formed between the other side plate section and the bottom plate section.Type: ApplicationFiled: June 3, 2014Publication date: February 16, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Keigo YAMAMOTO, Takashi ISHIDA
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Patent number: 9525062Abstract: An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.Type: GrantFiled: April 20, 2016Date of Patent: December 20, 2016Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takashi Ishida, Takashi Okawa
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Publication number: 20160339615Abstract: An FRP shaping jig has a main structure holding jig (22) and a reinforcement part holding jig (26A; 26D) with flexibility. The FRP shaping jig is used when a main structure (12) and a reinforcement part (14A; 14B) are joined to shape an FRP structure 10. The main structure holding jig (22) positions and holds the main structure (12) configured from a fiber component. The reinforcement part holding jig (26A; 26D) is positioned to the main structure holding jig (22) and positions and holds the reinforcement part (14A; 14B) while pushing the reinforcement part (14A; 14B) configured from a fiber component.Type: ApplicationFiled: January 27, 2015Publication date: November 24, 2016Inventors: Toshio ABE, Tetsuya KATO, Kiyoka TAKAGI, Takayuki KOYAMA, Katsuya YOSHINO, Kazuaki KISHIMOTO, Koichi SAITO, Takashi ISHIDA
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Publication number: 20160339668Abstract: A composite material structure is composed of a first face plate and a corrugated core bonded to the first face plate. The corrugated core has at least one opening.Type: ApplicationFiled: January 28, 2015Publication date: November 24, 2016Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Toshio ABE, Kiyoka TAKAGI, Takayuki KOYAMA, Katsuya YOSHINO, Kazuaki KISHIMOTO, Koichi SAITO, Takashi ISHIDA
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Publication number: 20160332395Abstract: A core (20) and a bag (22, 24) are provided which are used to shape an FRP structure (10; 30). The bag (22, 24) has a core bag section (24) which covers the outer circumference of the core (20), and a coverture bag section (22) which covers a plurality of fiber components (12, 14; 12, 14, 16).Type: ApplicationFiled: January 27, 2015Publication date: November 17, 2016Inventors: Toshio ABE, Kiyoka TAKAGI, Takayuki KOYAMA, Katsuya YOSHINO, Kazuaki KISHIMOTO, Koichi SAITO, Takashi ISHIDA
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Publication number: 20160315151Abstract: A semiconductor substrate includes: a first conduction type first semiconductor region exposed at a first surface; a second conduction type main base region exposed at the first surface at a position adjacent to the first semiconductor region; and a second conduction type surface layer base region which is exposed at the first surface at a position adjacent to the main base region and has a smaller thickness than that of the main base region. A gate electrode is disposed across upper portions of the first semiconductor region, the main base region, and the surface layer base region.Type: ApplicationFiled: April 15, 2016Publication date: October 27, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi ISHIDA, Takashi OKAWA
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Publication number: 20160315190Abstract: An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.Type: ApplicationFiled: April 20, 2016Publication date: October 27, 2016Inventors: Takashi Ishida, Takashi Okawa
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Publication number: 20160244140Abstract: Provided is a joint and an aircraft structure wherein it is possible to position a member relative to a preform with high accuracy. A groove into which a plate member (30) is inserted is formed in a pi-shaped joint (20) provided on the preform (21), and the preform (21) and the plate member (30) are connected by being bonded. Moreover, a fitting shape (32A-1) into which the plate member (30) is fitted is formed on the pi-shaped joint (20) on the whole groove bottom face. Additionally, a fitting shape (32A-2) into which the plate member (30) is fitted is formed on a portion of the groove bottom face. Furthermore, fitting shapes (32B-1, 32B-2), into which the groove bottom face that is formed on the pi-shaped joint (20) is fitted, are formed on the surface of the plate material (30) that is fitted with the pi-shaped joint (20).Type: ApplicationFiled: May 20, 2014Publication date: August 25, 2016Inventors: Toshio ABE, Kiyoka TAKAGI, Takayuki KOYAMA, Kazuaki KISHIMOTO, Kouichi SAITO, Takashi ISHIDA
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Publication number: 20160194071Abstract: A joint (20) joins a plate member (26) with a preform (22), wherein an inclined part (28), which is inclined relative to a surface that is orthogonal to the direction in which a tensile load is applied to the plate member (26), is formed on a surface (25) that joins with the preform (22). Moreover, an indented part (38) corresponding to the shape of the inclined part (28) is formed on the preform (22) so that the inclined part (28) of the joint (20) is embedded into the indented part (38). The joint (20) is embedded in and bonded to the preform (22). As a consequence, the strength of the bonding surface of the joint (20) and the preform (22) becomes greater.Type: ApplicationFiled: June 16, 2014Publication date: July 7, 2016Inventors: Toshio ABE, Kiyoka TAKAGI, Takayuki KOYAMA, Kazuaki KISHIMOTO, Kouichi SAITO, Takashi ISHIDA
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Publication number: 20150357343Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: September 11, 2014Publication date: December 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takashi ISHIDA, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
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Publication number: 20150222215Abstract: Provided is drive unit of a synchronous motor capable of improving the accuracy of magnetic flux operations with a simple configuration. To this end, the drive unit has a magnetic flux operation part which, in the case where a direction of a magnetic field pole of the synchronous motor is regarded as a d-axis and a direction orthogonal to the d-axis is regarded as a q-axis, calculates a magnetic flux of the d-axis and a magnetic flux of the q-axis on the basis of a current of the d-axis, a current of the q-axis, and a field current of the synchronous motor; and a magnetic flux operation error correcting part which calculates a phase difference between an input voltage and an input current of the synchronous motor and corrects an inner-phase difference angle calculated from the magnetic flux of the d-axis and the magnetic flux of the q-axis on the basis of the phase difference.Type: ApplicationFiled: September 3, 2012Publication date: August 6, 2015Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATIONInventor: Takashi Ishida
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Patent number: D782568Type: GrantFiled: February 18, 2015Date of Patent: March 28, 2017Assignee: RICOH COMPANY, LTD.Inventors: Yuta Nishimura, Takashi Ishida