Patents by Inventor Takashi Ishigaki

Takashi Ishigaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8183115
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Patent number: 8183635
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Shinichiro Kimura, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto
  • Patent number: 8143668
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Morita, Ryuta Tsuchiya, Takashi Ishigaki, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20120061774
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Inventors: Yusuke Morita, Ryuta Tsuchiya, Takashi Ishigaki, Nobuyuki Sugii, Shinichiro Kimura
  • Patent number: 8106557
    Abstract: It is an objective to provide a permanent magnet synchronous motor that is highly efficient with low vibration and low noise. A stator 30 includes a stator core 1 that includes magnetic pole teeth 2 each formed between adjacent slots 3, and stator windings 4 that are provided in the slots 3 of the stator core 1. A rotor 40 includes a rotor core 5, a plurality of magnet retaining holes 8, permanent magnets 7 inserted in the magnet retaining holes 8, and a plurality of slits 6 in the rotor core 5 on an outer circumferential side of the magnet retaining holes 8. Among the slits 6, slits 6 in a vicinity of a magnetic pole center of the rotor core 5 are oriented in a direction where a magnetic flux generated by a permanent magnet 7 converges outside the rotor core 5, whereas slits 6 in a vicinity of a pole border portion of the rotor core 5 are oriented in another direction that is different from the direction of the plurality of slits 6 in the vicinity of the magnetic pole center of the rotor core 5.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: January 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hayato Yoshino, Yoshio Takita, Koji Yabe, Takashi Ishigaki, Koji Masumoto
  • Publication number: 20120018807
    Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
    Type: Application
    Filed: January 18, 2010
    Publication date: January 26, 2012
    Applicant: HITACHI, LTD.
    Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
  • Publication number: 20110195566
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONCS CORPORATION
    Inventors: Takashi ISHIGAKI, Ryuta TSUCHIYA, Yusuke MORITA, Nobuyuki SUGII, Shinichiro KIMURA, Toshiaki IWAMATSU
  • Publication number: 20100258869
    Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Inventors: Yusuke MORITA, Ryuta Tsuchiya, Takashi Ishigaki, Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20100258871
    Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 14, 2010
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii
  • Publication number: 20100258872
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Inventors: Nobuyuki SUGII, Ryuta TSUCHIYA, Shinichiro KIMURA, Takashi ISHIGAKI, Yusuke MORITA, Hiroyuki YOSHIMOTO
  • Publication number: 20100117477
    Abstract: It is an objective to provide a permanent magnet synchronous motor that is highly efficient with low vibration and low noise. A stator 30 includes a stator core 1 that includes magnetic pole teeth 2 each formed between adjacent slots 3, and stator windings 4 that are provided in the slots 3 of the stator core 1. A rotor 40 includes a rotor core 5, a plurality of magnet retaining holes 8, permanent magnets 7 inserted in the magnet retaining holes 8, and a plurality of slits 6 in the rotor core 5 on an outer circumferential side of the magnet retaining holes 8. Among the slits 6, slits 6 in a vicinity of a magnetic pole center of the rotor core 5 are oriented in a direction where a magnetic flux generated by a permanent magnet 7 converges outside the rotor core 5, whereas slits 6 in a vicinity of a pole border portion of the rotor core 5 are oriented in another direction that is different from the direction of the plurality of slits 6 in the vicinity of the magnetic pole center of the rotor core 5.
    Type: Application
    Filed: February 21, 2007
    Publication date: May 13, 2010
    Applicant: Mitsubishi Electic Corporation
    Inventors: Hayato Yoshino, Yoshio Takita, Koji Yabe, Takashi Ishigaki, Koji Masumoto
  • Publication number: 20090309159
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 17, 2009
    Inventors: Yusuke MORITA, Ryuta TSUCHIYA, Takashi ISHIGAKI, Nobuyuki SUGII, Shinichiro KIMURA
  • Publication number: 20090096036
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 16, 2009
    Inventors: Takashi ISHIGAKI, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Publication number: 20070205440
    Abstract: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on the floating gate interposing a second gate insulation layer therebetween, a second gate electrode which extends in the first direction and which is formed on the second charge retaining region interposing the second gate insulation layer therebetween, and a semiconductor layer which extends in a second direction and which is formed on the semiconductor substrate so as to intersect the first and the second gate electrode are provided; wherein an n-type conductive region of a second conductive type is formed on the semiconductor layer. Consequently, it achieves high-integration of a semiconductor device.
    Type: Application
    Filed: December 19, 2006
    Publication date: September 6, 2007
    Inventors: Takashi Ishigaki, Taro Osabe, Takashi Kobayashi, Yutaka Imai, Masahiro Shimizu
  • Publication number: 20070176219
    Abstract: A plurality of floating gates are formed on a principal surface of a semiconductor substrate that constitutes a nonvolatile semiconductor memory device through a first gate dielectric film. An auxiliary gate formed on the principal surface of the semiconductor substrate through a third gate dielectric film is formed on one adjacent side of the floating gates. A groove is formed on the other adjacent side of the floating gate, and an n-type diffusion layer is formed on a bottom side of the groove. A data line of the nonvolatile semiconductor memory device is constituted by an inversion layer formed on the principal surface of the semiconductor substrate to be opposed to an auxiliary gate by applying desired voltage to the auxiliary gate, and the n-type diffusion layer.
    Type: Application
    Filed: December 19, 2006
    Publication date: August 2, 2007
    Inventors: Taro OSABE, Takashi Ishigaki, Yoshitaka Sasago
  • Patent number: 7038244
    Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: May 2, 2006
    Assignees: NEC Compound Semiconductor Devices, Ltd., NEC Corporation
    Inventors: Takashi Ishigaki, Takaki Niwa, Naoto Kurosawa, Hidenori Shimawaki
  • Publication number: 20050110045
    Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.
    Type: Application
    Filed: November 23, 2004
    Publication date: May 26, 2005
    Applicants: NEC Compound Semiconductor Devices, Ltd., NEC Corporation
    Inventors: Takashi Ishigaki, Takaki Niwa, Naoto Kurosawa, Hidenori Shimawaki