Patents by Inventor Takashi Ishioka
Takashi Ishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074056Abstract: A printed wiring board includes a multilayer substrate. The multilayer substrate includes a core layer and a build-up layer. The build-up layer is stacked on one surface of the core layer and constitutes a first surface of the multilayer substrate. The multilayer substrate is provided with a via conductor that penetrates through the core layer and the build-up layer in a thickness direction. The via conductor includes a filled via and a conformal via electrically connected to the filled via. At least part of the filled via overlaps the conformal via when viewed in the thickness direction and the filled via is positioned towards the first surface relative to the conformal via.Type: ApplicationFiled: November 24, 2021Publication date: February 29, 2024Applicant: KYOCERA CorporationInventors: Shinri SAEKI, Takashi ISHIOKA
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Patent number: 11903146Abstract: A printed wiring board is provided with: a core substrate corresponding to a stack area in which an interlayer connection conductor constituting an inner via is continuous; and a build-up layer comprising a resin layer stacked on the core substrate and a conductor layer on said resin layer. A via inner space inside the interlayer connection conductor constituting the inner via is hollow, and said via inner space communicates to the outside via a hole section provided in the build-up layer.Type: GrantFiled: May 29, 2020Date of Patent: February 13, 2024Assignee: Kyocera CorporationInventors: Tomoya Nagase, Takashi Ishioka
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Publication number: 20240040693Abstract: A printed wiring board includes a dielectric layer, a first and second conductor layer, and a plurality of via conductors. The dielectric layer has first and second opposing surfaces. The first and second conductor layer lie in the first second surfaces of the dielectric layer, respectively. Each via conductor extends through the dielectric layer and connects the first and second conductor layers to each other. Part of the printed wiring board is surrounded with the via conductors and is an overlap between the first conductor layer and the second conductor layer in a transparent plan view. When viewed in plan, the via conductors each have an aspect ratio greater than 1 and a major axis extending in a first direction and a minor axis extending in a second direction. The via conductors include a via conductor whose major axis extends and connects the via conductors arranged in a line.Type: ApplicationFiled: December 10, 2021Publication date: February 1, 2024Applicant: KYOCERA CorporationInventors: Atsuo KAWAGOE, Takashi ISHIOKA, Masanori NAITO, Nobuyuki UEDA
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Publication number: 20220232709Abstract: A printed wiring board is provided with: a core substrate corresponding to a stack area in which an interlayer connection conductor constituting an inner via is continuous; and a build-up layer comprising a resin layer stacked on the core substrate and a conductor layer on said resin layer. A via inner space inside the interlayer connection conductor constituting the inner via is hollow, and said via inner space communicates to the outside via a hole section provided in the build-up layer.Type: ApplicationFiled: May 29, 2020Publication date: July 21, 2022Applicant: KYOCERA CorporationInventors: Tomoya NAGASE, Takashi ISHIOKA
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Patent number: 10779408Abstract: The printed wiring board of the present disclosure includes: a plurality of insulating layers laminated in a thickness direction; a plurality of wiring conductors respectively correspondingly positioned between the plurality of insulating layers; a through hole penetrating the plurality of insulating layers and the plurality of wiring conductors in the thickness direction; and a through-hole conductor positioned on a wall surface of the through hole; each of the plurality of wiring conductors has a first surface facing the through hole, each of the plurality of insulating layers has a second surface facing the through hole, and the first surface is farther away from a central axis penetrating the through hole in the thickness direction than the second surface.Type: GrantFiled: September 19, 2019Date of Patent: September 15, 2020Assignee: KYOCERA CorporationInventors: Takashi Ishioka, Hidetoshi Yugawa
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Publication number: 20200120799Abstract: The printed wiring board of the present disclosure includes: a plurality of insulating layers laminated in a thickness direction; a plurality of wiring conductors respectively correspondingly positioned between the plurality of insulating layers; a through hole penetrating the plurality of insulating layers and the plurality of wiring conductors in the thickness direction; and a through-hole conductor positioned on a wall surface of the through hole; each of the plurality of wiring conductors has a first surface facing the through hole, each of the plurality of insulating layers has a second surface facing the through hole, and the first surface is farther away from a central axis penetrating the through hole in the thickness direction than the second surface.Type: ApplicationFiled: September 19, 2019Publication date: April 16, 2020Applicant: KYOCERA CorporationInventors: Takashi ISHIOKA, Hidetoshi YUGAWA
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Patent number: 9402309Abstract: The printed wiring board includes: an insulating board including a conductive metal layer formed on both surfaces of an insulating resin; and a conductor layer formed on both surfaces of the insulating board, the conductor layer including a different circuit pattern depending on a region. The circuit patterns formed on both surfaces of the insulating board includes a pattern with line width accuracy of ±10 ?m or less, and a conductor layer thickness in a region having a dense circuit pattern area and a conductor layer thickness in a region having a sparse circuit pattern area have a following relational expression: conductor layer thickness in a dense region/conductor layer thickness in a sparse region=0.7 to 1.0.Type: GrantFiled: June 25, 2015Date of Patent: July 26, 2016Assignee: Kyocera CorporationInventors: Shinri Saeki, Takashi Ishioka, Satoshi Nakamura
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Publication number: 20150382458Abstract: The printed wiring board includes: an insulating board including a conductive metal layer formed on both surfaces of an insulating resin; and a conductor layer formed on both surfaces of the insulating board, the conductor layer including a different circuit pattern depending on a region. The circuit patterns formed on both surfaces of the insulating board includes a pattern with line width accuracy of ±10 ?m or less, and a conductor layer thickness in a region having a dense circuit pattern area and a conductor layer thickness in a region having a sparse circuit pattern area have a following relational expression: conductor layer thickness in a dense region/conductor layer thickness in a sparse region=0.7 to 1.0.Type: ApplicationFiled: June 25, 2015Publication date: December 31, 2015Applicant: KYOCERA Circuit Solutions, Inc.Inventors: Shinri SAEKI, Takashi ISHIOKA, Satoshi NAKAMURA
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Publication number: 20120240090Abstract: A clock tree designing apparatus in an embodiment includes: an equidistant point set calculation section configured to set a path setting block area in which a path length of a clock path takes a shortest Manhattan distance and determine a set of equidistant points between a target sink and a farthest sink; a branch point setting section configured to set, as a branch point, a point in the set of equidistant points that is farthest from a clock source within the path setting block area; and a path setting section configured to set a shared path for the target sink and the farthest sink within the path setting block area from the clock source to the branch point, and to set a clock path from the branch point to the target sink or the farthest sink.Type: ApplicationFiled: September 1, 2011Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiaki SHIRAI, Takashi ISHIOKA
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Publication number: 20110260764Abstract: A method for designing a semiconductor integrated circuit according to an embodiment includes: placing standard flip-flop circuits and low power-consumption flip-flop circuits; grouping the placed flip-flop circuits into clusters by using an evaluation function having indices including cell types; assigning a first clock buffer to each cluster formed only by standard flip-flop circuits; assigning a second clock buffer to each cluster including low power-consumption flip-flop circuits, the second clock buffer having a larger size than the first clock buffer; and performing clock wiring.Type: ApplicationFiled: November 24, 2010Publication date: October 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi KITAHARA, Takashi ISHIOKA, Toshiaki SHIRAI
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Patent number: 7230554Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.Type: GrantFiled: April 26, 2006Date of Patent: June 12, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
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Publication number: 20060197695Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.Type: ApplicationFiled: April 26, 2006Publication date: September 7, 2006Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
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Patent number: 7075336Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.Type: GrantFiled: June 28, 2002Date of Patent: July 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Naohito Kojima, Fumihiro Minami, Masami Murakata, Takashi Ishioka
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Patent number: 7064691Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.Type: GrantFiled: August 7, 2002Date of Patent: June 20, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
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Patent number: 6813756Abstract: With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.Type: GrantFiled: October 24, 2002Date of Patent: November 2, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
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Publication number: 20030079194Abstract: With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.Type: ApplicationFiled: October 24, 2002Publication date: April 24, 2003Inventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
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Patent number: 6546540Abstract: With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.Type: GrantFiled: November 15, 2000Date of Patent: April 8, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka
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Publication number: 20030011500Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.Type: ApplicationFiled: August 7, 2002Publication date: January 16, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
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Publication number: 20030014724Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.Type: ApplicationFiled: June 28, 2002Publication date: January 16, 2003Inventors: Naohito Kojima, Fumihiro Minami, Masami Murakata, Takashi Ishioka
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Patent number: 6459331Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.Type: GrantFiled: September 2, 1998Date of Patent: October 1, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi