Patents by Inventor Takashi Ishioka

Takashi Ishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device manufacturing method by carrying out logic design
    Patent number: 5913101
    Abstract: In order to modify a combination of logic gates based on relationships between physical locations of the logic gates in a semiconductor integrated circuit which has already been subjected to layout design in the middle of design of the semiconductor integrated circuit, circuit portions whose combination is to be modified are specified, then the circuit portions are transformed into logically equivalent intermediate representations (NAND2s, IVs, etc.), then anew combination of the logic gates is generated based on the intermediate representation, and then the prior combination of the logic gates is replaced with the new combination of the logic gates.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: June 15, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Murofushi, Takashi Ishioka