Patents by Inventor Takashi Iwase

Takashi Iwase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366282
    Abstract: When a start condition determined in advance is satisfied while a vehicle is parked, a controller controls an aircraft such that the aircraft takes off from the vehicle, a photographing unit captures a position notification image including at least the vehicle and notifying a parking position of the vehicle, and the position notification image is transmitted to a mobile terminal having a display unit and carried by a user outside the vehicle.
    Type: Application
    Filed: March 10, 2021
    Publication date: November 25, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Hironobu HASHIGUCHI, Takashi IWASE, Akira YASUTAKE, Tsuyoshi ARINAGA
  • Publication number: 20210282992
    Abstract: A wheelchair includes a seating portion on which a wheelchair user sits, a body frame that supports the seating portion, a pair of rear wheels and a pair of front wheels rotatably supported by the body frame, and a seat back portion capable of changing the inclination angle with respect to the seating portion. The wheelchair includes push-along handle portions as engaging portions capable of fixing the seat back portion to a side sill as a vehicle body member that forms a door opening of the vehicle when the seat back portion is tilted backward of the wheelchair.
    Type: Application
    Filed: February 12, 2021
    Publication date: September 16, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Takashi IWASE, Isao TODA
  • Publication number: 20210282988
    Abstract: The wheelchair includes a pair of body frames and, wheels, cross bars, and a seating portion. The wheels are supported rotatably with respect to the pair of body frames by the pair of body frames. The cross bars are provided so as to extend in the Y-direction across the pair of body frames. The seating portion is attached to the pair of body frames and is the portion on which the wheelchair user sits. In the wheelchair, the body frame and the body frame are movable in the longitudinal direction of the cross bars, respectively. The distance between the body frame and the body frame can be changed by moving the body frames in the longitudinal direction of the cross bars.
    Type: Application
    Filed: February 17, 2021
    Publication date: September 16, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Takashi IWASE, Isao TODA
  • Publication number: 20210282989
    Abstract: The wheelchair includes a seating portion, body frames that support the seating portion, wheels that are rotatably supported by the body frames, an engaging portion, a left brake that brakes a left rear wheel, and a coupling portion that couples the engaging portion and the left brake to each other. The engaging portion is capable of switching between an engagement attitude for engaging a vehicle body member that forms an opening of a vehicle and a disengagement attitude for releasing the engagement with the vehicle body member. The coupling portion transmits the movement of the engaging portion to the left brake when the engaging portion makes an attitude change from the disengagement attitude to the engagement attitude. This operates the left brake when the attitude of the engaging portion switches from the disengagement attitude to the engagement attitude and brakes the left rear wheel.
    Type: Application
    Filed: February 12, 2021
    Publication date: September 16, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Takashi IWASE, Isao TODA, Akira YASUTAKE, Tsuyoshi ARINAGA
  • Patent number: 10665271
    Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: May 26, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Takeda, Takashi Iwase
  • Publication number: 20190172503
    Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.
    Type: Application
    Filed: October 3, 2018
    Publication date: June 6, 2019
    Inventors: Koichi TAKEDA, Takashi IWASE
  • Patent number: 10255956
    Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Iwase, Ken Matsubara
  • Patent number: 10192621
    Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Matsubara, Takashi Iwase, Satoru Nakanishi
  • Publication number: 20180233181
    Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.
    Type: Application
    Filed: December 18, 2017
    Publication date: August 16, 2018
    Inventors: Takashi IWASE, Ken MATSUBARA
  • Publication number: 20180197609
    Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Ken MATSUBARA, Takashi IWASE, Satoru NAKANISHI
  • Patent number: 9947409
    Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ken Matsubara, Takashi Iwase, Satoru Nakanishi
  • Publication number: 20170351312
    Abstract: There is to provide a semiconductor device capable of storing save data at a shutdown of a power. The semiconductor device of receiving the power includes a memory unit having a plurality of memory cells capable of storing data, a power detecting circuit that detects shutdown of the power, and a condenser capable of temporarily supplying an operation voltage, instead of the power, at the power shutdown. The memory unit includes a voltage generating unit that generates a plurality of writing voltages based on the operation voltage from the condenser at the power shutdown and a writing circuit that performs data writing of save data for a plurality of memory cells, based on the writing voltages generated by the voltage generating unit.
    Type: Application
    Filed: April 7, 2017
    Publication date: December 7, 2017
    Inventors: Takashi Iwase, Ken Matsubara, Hidenori Mitani, Hiroshi Sato
  • Publication number: 20170236587
    Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 17, 2017
    Inventors: Ken MATSUBARA, Takashi IWASE, Satoru NAKANISHI
  • Patent number: 8441880
    Abstract: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. An operational stability of the nonvolatile memory is realized.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toru Matsushita, Ken Matsubara, Takashi Iwase, Hidenori Mitani, Jun Setogawa, Fumiko Yamada
  • Patent number: 8335112
    Abstract: A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: December 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kono, Ken Matsubara, Takashi Iwase
  • Patent number: 8144518
    Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
  • Publication number: 20120002498
    Abstract: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Inventors: Toru Matsushita, Ken Matsubara, Takashi Iwase, Hidenori Mitani, Jun Setogawa, Fumiko Yamada
  • Publication number: 20110288807
    Abstract: The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 24, 2011
    Inventors: Takashi Iwase, Masamichi Fujito
  • Publication number: 20110208904
    Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
  • Patent number: 7957195
    Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji