Patents by Inventor Takashi Iwase
Takashi Iwase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8335112Abstract: A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.Type: GrantFiled: April 23, 2010Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Kono, Ken Matsubara, Takashi Iwase
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Patent number: 8144518Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: May 3, 2011Date of Patent: March 27, 2012Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20120002498Abstract: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.Type: ApplicationFiled: June 29, 2011Publication date: January 5, 2012Inventors: Toru Matsushita, Ken Matsubara, Takashi Iwase, Hidenori Mitani, Jun Setogawa, Fumiko Yamada
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Publication number: 20110288807Abstract: The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected.Type: ApplicationFiled: May 19, 2011Publication date: November 24, 2011Inventors: Takashi Iwase, Masamichi Fujito
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Publication number: 20110208904Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Patent number: 7957195Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: December 3, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Patent number: 7943124Abstract: The present invention relates to a composition for immunostimulation useful for promoting IgA and secretory component productions in mucosal tissues, comprising, alone or in combination, a cell of bifidobacterium belonging to Bifidobacterium bifidum or a processed product thereof, wherein the bifidobacterium has an activity to stimulate secretory component production and a high activity to stimulate IgA production, for example, it is a Bifidobacterium bifidum OLB 6377 strain or Bifidobacterium bifidum OLB 6378 strain.Type: GrantFiled: February 1, 2006Date of Patent: May 17, 2011Assignee: Meiji Dairies CorporationInventors: Itaru Moro, Takashi Iwase, Kuniyasu Ochiai, Masako Yajima, Masaki Terahara, Yoshitaka Nakamura, Mamoru Totsuka, Kiyoshi Yamada
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Publication number: 20100290290Abstract: A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.Type: ApplicationFiled: April 23, 2010Publication date: November 18, 2010Inventors: Takashi KONO, Ken Matsubara, Takashi Iwase
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Publication number: 20100080058Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Patent number: 7646642Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: October 9, 2007Date of Patent: January 12, 2010Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Publication number: 20090142374Abstract: The present invention relates to a composition for immunostimulation useful for promoting IgA and secretory component productions in mucosal tissues, comprising, alone or in combination, a cell of bifidobacterium belonging to Bifidobacterium bifidum or a processed product thereof, wherein the bifidobacterium has an activity to stimulate secretory component production and a high activity to stimulate IgA production, for example, it is a Bifidobacterium bifidum OLB 6377 strain or Bifidobacterium bifidum OLB 6378 strain.Type: ApplicationFiled: February 1, 2006Publication date: June 4, 2009Applicant: MEIJI DAIRIES CORPORATIONInventors: Itaru Moro, Takashi Iwase, Kuniyasu Ochiai, Masako Yajima, Masaki Terahara, Yoshitaka Nakamura, Mamoru Totsuka, Kiyoshi Yamada
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Publication number: 20080089146Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: October 9, 2007Publication date: April 17, 2008Inventors: Masamichi FUJITO, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
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Patent number: 5616079Abstract: An objective of the present invention is to provide a 3D games machine that can form a high-quality pseudo-3D image in real time. Segmented map information relating to a map that configures a game space is stored in a map information storage unit (110). This segmented map information contains map position information and an object number. A game space setting unit (104) reads out image information on the map from an object image information storage unit (120) on the basis of this object number, to set the games space. In this case, a plurality of types of segmented map information, of different numbers of segments, is stored in the map information storage unit (110). The game space setting unit (104) sets the game space by reading out segmented map information with a smaller number of segments as the distance between the vehicle operated by the player and the segmented map increases.Type: GrantFiled: February 15, 1995Date of Patent: April 1, 1997Assignee: Namco Ltd.Inventors: Takashi Iwase, Takashi Matsumoto, Nobuyuki Aoshima, Norimasa Matsuura, Takashi Goto