Abstract: A method of exchanging information in a processing system including the steps of storing the internal state information of a first arithmetic processing unit upon occurrence of a fault into a system control unit, sending a processor relief instruction from the system control unit to a second arithmetic processing unit, suppressing the updating of the internal state information of the second arithmetic processing unit, storing the internal state information of the second processing unit into the system control unit, transferring the internal state information of the first arithmetic processing unit from the system control unit to the second arithmetic processing unit, and sending a reset and actuating signal from the system control unit to the second arithmetic processing unit.

Abstract: A method of exchanging information in a processing system including the steps of issuing a clock synchronizing instruction from an operating system, holding the clock synchronizing instruction in a communication information holding unit, suppressing the updating of internal state information in a first arithmetic unit in response to the holding signal, outputting a communication demand signal from the communication information holding unit to a system control unit, freezing the updating of the calendar clock values in respective first and second arithmetic processing units, receiving in the system control unit the first clock value from the first arithmetic processing unit, storing the first calendar clock value in the second arithmetic processing unit, issuing a restarting signal to the arithmetic processing units, and issuing a microprogram actuating instruction to the arithmetic processing units from the system control unit.

Abstract: An information processing system comprises at least one arithmetic processing unit operating under the control of a microprogram and a system control unit which exchanges information with the arithmetic processing unit. The system control unit is not required to perform distinction processing between one source of interruption, for example a fault notice, and another source of interruption, for example a clock synchronization demand.

Abstract: For a plurality of logic units which are organized into scan-path groups, a scan-path self-testing circuit is provided which comprises a clock source and a plurality of gates for supplying the clock pulse to the logic units when selectively enabled. To give flexibility to group organization of the logic units, the gates are provided in a one-to-one relationship with the logic units. Bit positions of a register are associated respectively with the gates. A scan path controller selects one of the scan-path groups and writes a logic 1 into the register bit positions which are associated with the logic units of the selected scan-path group.

Abstract: A memory initialization system for initializing a memory content in response to a memory initialization instruction is disclosed. In this system, a memory initialization instruction validity control means for controlling validity of the memory initialization instruction is arranged. The memory initialization instruction validity control means can render the memory initialization instruction invalid so as to inhibit initialization for the memory.

Abstract: In an electronic circuit for dividing a dividend (RR) by a divisor (RD) to calculate an eventual quotient (Q) divisible into first through N-th partial quotients, each being represented by a g-ary number, an approximate reciprocal (RC) of the divisor is read out of a memory (34) and multiplied in a first multiplication circuit (36) by the divisor to obtain a correction factor (C.sub.1). A second multiplication circuit (37) multiplies the dividend by the approximate reciprocal to calculate a first provisional quotient which is near to the eventual quotient and which is processed into a first partial provisional quotient (P.sub.1) and a second provisional quotient by a first adder circuit (61) and a second partial divider (64.sub.1), respectively. The first partial provisional quotient is modified into the first partial quotient Q.sub.1 with reference to the second provisional quotient in a first correction circuit (66.sub.1). Likewise, an i-th partial quotient (Q.sub.