Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: A jointing structure comprising multiple steps provided face to face at the coaxially built traveling path ends with an expansion gap between, multiple elastic members respectively mounted inside the multiple steps, and a joint block mounted on the multiple elastic members across the expansion gap. Multiple supporting blocks and one or more than one intermediate joint block are mounted inside the multiple steps with the joint block between. The multiple supporting blocks, the joint block and the one or more than one intermediate joint block are of concrete. The elastic members are joined together across the expansion gap. The elastic member on one side is fixed to the inside of the step on one side and then subjected to deformation toward the bridge girder axis, and thereafter, the elastic member on the other side is fixed to the inside of the step on the other side.

Abstract: A plug receptacle includes a housing having at least one outlet unit to which a plug is adapted to be connected to supply a DC power to the plug, and a cable, connected to the housing, for supplying the DC power to the housing. The outlet unit includes a plug-receiving portion having a plurality of substantially circular pin-inserting holes into which plug pins of the plug are inserted and an insertion groove formed to surround a periphery of the plug-receiving portion. The plug-receiving portion has a substantially quadrangular shape viewed from a front side thereof. The insertion groove is adapted to receive a surrounding wall of the plug and has a substantially quadrangular shape viewed from the front side. The pin-receiving holes are arranged along one side of the plug-receiving portion serving as a reference side and offset closer to the reference side than an opposite side to the reference side.

Abstract: A plug is adapted to be connected to a DC outlet to supply a DC power to the plug. The plug includes plug pins and a substantially quadrangular-shaped surrounding wall for surrounding the plug pins. The DC outlet includes: an outlet main body having an outlet unit to which the plug is adapted to be connected. The outlet unit includes a plug-receiving portion having pin-inserting holes into which the plug pins are inserted; an insertion groove formed to surround a periphery of the plug-receiving portion, the insertion groove being adapted to receive the surrounding wall; and pin-receiving pieces for being connected with the plug pins that are respectively inserted through the pin-receiving holes. Two pin-receiving holes corresponding to the pin-receiving pieces are arranged along a reference side of the plug- receiving portion and offset closer to the reference side than an opposite side to the reference side.

Abstract: A plug, adapted to be connected to a direct current (DC) outlet for supplying a DC power thereto, includes a plurality of round bar-shaped plug pins which protrudes from a front surface of a plug main body, and a surrounding wall which protrudes from the front surface of the plug main body to surround the plug pins. The plug pins are adapted to be connected the pin-receiving pieces through pin insertion holes of the DC outlet and to be supplied with power from the DC outlet. The surrounding wall is adapted to be inserted into an insertion groove of the DC outlet which is formed around the pin-insertion holes. The surrounding wall is formed in a substantially quadrangular shape, viewed from a front side thereof. The plug pins are arranged along a reference surface corresponding to one inner surface of the surrounding wall and offset closer to the reference surface than to an inner surface opposite to the reference surface.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: A adhered substance removing device of the present disclosure includes a suction removal unit configured to suck and remove a liquid medium with which a wiping sheet is impregnated and adhered substances which is separated from the wiping sheet by an oscillation unit and re-adhered to a surface of the wiping sheet. The suction removal unit includes a cylindrical suction nozzle having inlet holes in a surface along which the wiping sheet is guided. and a suction pump configured to suck air from the suction nozzle. The Suction pump is connected to the suction nozzle, and a lid is detachably attached to an opening of the suction nozzle.

Abstract: A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting device for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.

Abstract: A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Abstract: A semiconductor chip area is reduced and the possibility of malfunction in generation of reproduction data and a reproduction clock is reduced. A transceiver comprises a clock data recovery circuit, a deserializer, a serializer, a PLL circuit, and a frequency detector. The clock data recovery circuit extracts a reproduction clock and reproduction data in response to a receive signal and a clock signal generated by the PLL circuit. The deserializer generates parallel receive data from the reproduction clock and the reproduction data, and the serializer generates a serial transmit signal from parallel transmit data and the clock signal. The detector detects a difference in frequency of the receive signal and the clock signal, and generates a frequency control signal. In response to the frequency control signal, the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency.

Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Abstract: Disclosed is a semiconductor IC device using a low-price oscillator, which is capable of bidirectional communication with a host and features a low price. In bidirectional communication between a host and a device, the device comprises a synchronization establishment unit, a frequency difference detector, a frequency generator, and an oscillator providing a reference signal. The synchronization establishment unit to which an output signal from the host is inputted outputs a received signal, a synchronization establishment signal and a reception data. The frequency difference detector detects a frequency difference between a received signal and a transmitting signal, and outputs a frequency coordination signal to the frequency generator. The number of frequency division of the frequency generator is controlled by the frequency coordination signal, and the frequency generator is capable of matching the frequency of the transmitting signal which is an output signal with the frequency of the received signal.

Abstract: Disclosed are a high-efficiency power amplifier and base station device with respect to high-speed, broadband radio communication method. A broadband power supply circuit includes a linear voltage amplifier to which an input signal is applied, a resistor connected to an output side of the linear voltage amplifier, a switching regulator amplifying the voltage difference between both ends of the resistor to convert the amplified voltage difference into current, and a high frequency amplifier. The high frequency amplifier is designed to exhibit high efficiency at a frequency band where the efficiency of the switching regulator starts to be deteriorated, or at a high frequency band where the operation of the linear amplifier is dominant. In this case, the amplification of low frequency components are performed by the switching regulator, and the amplification of high frequency components are performed by the linear amplifier and the high frequency amplifier.

Abstract: A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting means for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.