Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: Disclosed are a high-efficiency power amplifier and base station device with respect to high-speed, broadband radio communication method. A broadband power supply circuit includes a linear voltage amplifier to which an input signal is applied, a resistor connected to an output side of the linear voltage amplifier, a switching regulator amplifying the voltage difference between both ends of the resistor to convert the amplified voltage difference into current, and a high frequency amplifier. The high frequency amplifier is designed to exhibit high efficiency at a frequency band where the efficiency of the switching regulator starts to be deteriorated, or at a high frequency band where the operation of the linear amplifier is dominant. In this case, the amplification of low frequency components are performed by the switching regulator, and the amplification of high frequency components are performed by the linear amplifier and the high frequency amplifier.

Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

Abstract: A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: Disclosed is a semiconductor IC device using a low-price oscillator, which is capable of bidirectional communication with a host and features a low price. In bidirectional communication between a host and a device, the device comprises a synchronization establishment unit, a frequency difference detector, a frequency generator, and an oscillator providing a reference signal. The synchronization establishment unit to which an output signal from the host is inputted outputs a received signal, a synchronization establishment signal and a reception data. The frequency difference detector detects a frequency difference between a received signal and a transmitting signal, and outputs a frequency coordination signal to the frequency generator. The number of frequency division of the frequency generator is controlled by the frequency coordination signal, and the frequency generator is capable of matching the frequency of the transmitting signal which is an output signal with the frequency of the received signal.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract: A sintered Fe alloy for a valve seat is made of a prepared powdery alloy which comprises C of from 0.3 wt. % to 1.6 wt. %, Cu of from 5 wt. % to 20 wt. %, hard particle of from 5 wt. % to 40 wt. % which consists of at least one species selected from ferroalloy, ceramic and intermetallic compound, and a balance which is a powdery Fe atomizing alloy containing at least one species of from 1 wt. % to 8 wt. % selected from Cr and Mo. The prepared powdery alloy containing the above-mentioned component and content is subject to a press forming process by a compression molding to form a green compact body which is then sintered. The sintered Fe alloy has a high thermal conductivity, a high strength at a high temperature and an excellent abrasion resistance, and, moreover, can be used for a valve seat provided in a high function engine.

Abstract: The invention is directed to an iron series sintered alloy superior in abrasion resistance, preferably usable for slipping parts such as valve seats used in internal combustion engines, vanes in compressors and so forth. The sintered alloy is of base matrix of a mixed structure comprising the primary phase of in area ratio 30.about.95% mainly of Fe having a hardness of 400 Hv or above with precipitated fine carbide of 10 .mu.m or smaller, and the secondary phase of in area ratio 5.about.70% softer than said primary phase, consisted of pure iron or carbon steel or low alloy steel. This base matrix will include in area ratio 1.about.20% infiltrated or previously added Cu phase or Cu alloy phase, or will include dispersed therein in area ratio 1.about.20% hard particles having average diameter of 20.about.100 .mu.m and a hardnessof 700.about.1500 Hv such as Fe--Mo paricles, Cr--Mo--Co intermetallic compound particles, C--Cr--W--Co particles, etc.

Abstract: A cylinder lock has a cylinder lock holder with a rotor rotatably disposed therein. The rotor has a plurality of grooves, with a plurality of tumblers slidably disposed in the grooves. Holder grooves are provided in the cylinder lock holder for receiving the tumblers projecting out of the grooves of the rotor. The rotor is able to be rotated in the cylinder lock holder in response to the insertion of a key into the rotor by causing the tumblers to be retracted from the holder grooves. Rotation is disabled when the key is removed, the tumblers projecting back into the holder grooves under the action of a spring biasing the tumblers. The key is inserted through a plurality of key insertion holes in the tumblers. Tooth portions are formed at respective contact portions between the tumblers and the inner surface of the cylinder lock holder, the respective tooth portions being engaged with each other when the key is removed from the lock.

Abstract: A sintered body is produced by a process comprising the steps of mixing one or more metal powder particles with an organic binder, injection-molding the mixture to form a green body of a predetermined shape, removing the binder from the green body to form a porous body substantially made of the metal powder, and heating the porous body to a sintering temperature and holding it at that temperature to produce a sintered body, in which process the binder is removed through the sequence of the following steps: preheating the green body in an inert gas atmosphere in a temperature range that creates open pores in it; placing the green body, in which open pores have started to form, in a hydrogen gas atmosphere optionally mixed with an inert gas; holding the green body in a temperature range where the metal powder is not carburized and where the open pores will be maintained, so that the greater part of the binder is removed to form a porous body that is substantially made of the metal powder alone; and further hold

Abstract: The present invention is directed toward an orthopedically improved chair that is designed so as to prevent pain in the waist or back of the user. In one embodiment of the present invention, the chair is adaptable for use as either a squat chair or a conventional type chair. The chair of this embodiment is characterized by a seat that is freely forwardly downwardly inclinable to a point about 20.degree. below the horizontal; and a forwardly protruding cross-bar portion that provides support for the lumbar region of the spine. In addition, this chair can be adapted for use as a conventional type chair by merely moving the downwardly inclinable seat into its vertical position and then using the base of the chair as a seat.