Patents by Inventor Takashi Kumamoto
Takashi Kumamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220176887Abstract: An interior structure of a vehicle door includes a door interior panel 11 and a bezel garnish 16. The door interior panel 11 is attached to a compartment inner side of a door inner panel. The bezel garnish 16 is attached to a periphery of an opening formed in the door interior panel 11. In the bezel garnish 16, a locking part to which a speaker grill 17 of a door speaker and a cover-shaped auxiliary interior panel are selectively attachable is provided.Type: ApplicationFiled: November 28, 2021Publication date: June 9, 2022Applicant: Honda Motor Co., Ltd.Inventors: Takashi KUMAMOTO, Keita ISHIZAKA, Takuya Okano
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Patent number: 11173535Abstract: A drilling jig for drilling a punching hole with a boundary between a basis material and a coating of a workpiece less noticeable, and a drilling method using this drilling jig. It includes a male blade, a female blade, and a hexagon bolt; the male blade and the hexagon bolt are capable of being coupled to each other; a screw hole, through which the hexagon bolt is inserted, and a blade portion are formed in the male blade; the blade portion has a planar blade surface; a shaft insertion hole, through which the hexagon bolt is inserted, and a blade portion housing hole capable of housing the blade portion are formed in the female blade, whereby the boundary between the basis material and the coating of a bumper can be positioned on the inside of the punching hole, preventing the appearance of the punching hole from being impaired.Type: GrantFiled: February 13, 2018Date of Patent: November 16, 2021Assignee: HONDA ACCESS CORP.Inventors: Shoji Yokoyama, Tomohiro Ogawa, Kazuya Takita, Ichiro Hosoya, Takashi Kumamoto, Yukio Kimura
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Publication number: 20190388951Abstract: A drilling jig for drilling a punching hole with a boundary between a basis material and a coating of a workpiece less noticeable, and a drilling method using this drilling jig. It includes a male blade, a female blade, and a hexagon bolt; the male blade and the hexagon bolt are capable of being coupled to each other; a screw hole, through which the hexagon bolt is inserted, and a blade portion are formed in the male blade; the blade portion has a planar blade surface; a shaft insertion hole, through which the hexagon bolt is inserted, and a blade portion housing hole capable of housing the blade portion are formed in the female blade, whereby the boundary between the basis material and the coating of a bumper can be positioned on the inside of the punching hole, preventing the appearance of the punching hole from being impaired.Type: ApplicationFiled: February 13, 2018Publication date: December 26, 2019Applicant: HONDA ACCESS CORP.Inventors: Shoji Yokoyama, Tomohiro Ogawa, Kazuya Takita, Ichiro Hosoya, Takashi Kumamoto, Yukio Kimura
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Patent number: 10224290Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.Type: GrantFiled: December 24, 2015Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Rajendra Dias, Takashi Kumamoto, Yoshishiro Tomita, Mitul Modi, Joshua Heppner, Eric Li
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Publication number: 20170186697Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Rajendra Dias, Takashi Kumamoto, Yoshishiro Tomita, Mitul Modi, Joshua Heppner, Eric Li
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Patent number: 8969134Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.Type: GrantFiled: May 10, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
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Publication number: 20140335686Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Inventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
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Patent number: 7145226Abstract: This invention relates to an apparatus and methods for increasing the microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.Type: GrantFiled: June 30, 2003Date of Patent: December 5, 2006Assignee: Intel CorporationInventor: Takashi Kumamoto
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Patent number: 7138709Abstract: This invention relates to an apparatus and method for increasing microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.Type: GrantFiled: September 15, 2003Date of Patent: November 21, 2006Assignee: Intel CorporationInventor: Takashi Kumamoto
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Patent number: 7132311Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.Type: GrantFiled: July 26, 2002Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Masayuki Akiba, Kinya Ichikawa, Jiro Kubota, Takashi Kumamoto
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Patent number: 7132739Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.Type: GrantFiled: October 28, 2004Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Masayuki Akiba, Kinya Ichikawa, Jiro Kubota, Takashi Kumamoto
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Patent number: 7071572Abstract: Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.Type: GrantFiled: August 3, 2004Date of Patent: July 4, 2006Assignee: Intel CorporationInventor: Takashi Kumamoto
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Publication number: 20050085034Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.Type: ApplicationFiled: October 28, 2004Publication date: April 21, 2005Inventors: Masayuki Akiba, Kinya Ichikawa, Jiro Kubota, Takashi Kumamoto
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Publication number: 20050006767Abstract: Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.Type: ApplicationFiled: August 3, 2004Publication date: January 13, 2005Inventor: Takashi Kumamoto
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Patent number: 6838313Abstract: A method for producing a molded flip chip package is described. According to one embodiment, an incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold, and a resin is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate, and the resin is cured by maintaining the mold at an elevated temperature for a predetermined amount of time.Type: GrantFiled: July 10, 2003Date of Patent: January 4, 2005Assignee: Intel CorporationInventors: Takashi Kumamoto, Kinya Ichikawa
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Publication number: 20040262729Abstract: This invention relates to an apparatus and method for increasing microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.Type: ApplicationFiled: September 15, 2003Publication date: December 30, 2004Inventor: Takashi Kumamoto
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Publication number: 20040262733Abstract: This invention relates to an apparatus and methods for increasing the microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventor: Takashi Kumamoto
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Patent number: D837118Type: GrantFiled: November 14, 2016Date of Patent: January 1, 2019Assignee: Honda Motor Co., Ltd.Inventors: Leonard Takada, Takashi Kumamoto
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Patent number: D1036336Type: GrantFiled: November 26, 2021Date of Patent: July 23, 2024Assignee: HONDA MOTOR CO., LTD.Inventor: Takashi Kumamoto
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Patent number: D1036337Type: GrantFiled: November 26, 2021Date of Patent: July 23, 2024Assignee: HONDA MOTOR CO., LTD.Inventors: Takashi Kumamoto, Fumi Jo