Patents by Inventor Takashi Kyono

Takashi Kyono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170294547
    Abstract: A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order. In the contact layer, a region including a first main surface that is a main surface on a quantum well structure side has a p-type impurity concentration lower than a p-type impurity concentration of a region including a second main surface that is a main surface opposite to the first main surface. A photodiode includes the semiconductor layered structure and an electrode formed on the semiconductor layered structure. A sensor includes the photodiode and a read-out circuit connected to the photodiode.
    Type: Application
    Filed: October 21, 2015
    Publication date: October 12, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kaoru SHIBATA, Koji NISHIZUKA, Suguru ARIKATA, Takashi KYONO, Katsushi AKITA
  • Patent number: 9773932
    Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 26, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Koji Nishizuka, Takashi Kyono, Kaoru Shibata, Katsushi Akita
  • Publication number: 20170141531
    Abstract: An optical module 1 according to an embodiment includes a plurality of laser diodes (LDs) 21 to 23, a multiplexing optical system 30 combining a plurality of laser beams from the respective plurality of LDs, and a package 10 accommodating the plurality of LDs and the multiplexing optical system. The package includes a support mounted with the plurality of LDs and the multiplexing optical system, and a cap having a transmissive window that allows a resultant light beam to pass through. At least one of the LDs has an oscillation wavelength of nor more than 550 nm. The package has an internal moisture content of not more than 3000 ppm. The multiplexing optical system is fixed to the support by a resin curing adhesive.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 18, 2017
    Inventors: Takashi Kyono, Hideyuki Ijiri, Takao Nakamura, Hiromi Nakanishi, Takatoshi Ikegami, Kuniaki Ishihara, Yohei Enya, Tetsuya Kumano
  • Patent number: 9608148
    Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Kei Fujii, Katsushi Akita
  • Publication number: 20170040477
    Abstract: A semiconductor layered structure according to the present invention includes a substrate formed of a III-V compound semiconductor; and semiconductor layers disposed on the substrate and formed of III-V compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm?3 or more and 2×1020 cm?3 or less, and the impurity has an activation ratio of 30% or more.
    Type: Application
    Filed: December 17, 2014
    Publication date: February 9, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Suguru Arikata, Takashi Kyono, Koji Nishizuka, Kaoru Shibata, Katsushi Akita
  • Publication number: 20160380137
    Abstract: A light-receiving device includes: a group III-V compound semiconductor substrate having a first main surface; and a light-receiving layer formed on the first main surface, and the group III-V compound semiconductor substrate has a dislocation density of 10000 cm?2 or less. Accordingly, the light-receiving device with low dark current is provided.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 29, 2016
    Inventors: Kaoru SHIBATA, Kei FUJII, Takashi KYONO, Koji NISHIZUKA, Katsushi AKITA
  • Publication number: 20160351742
    Abstract: A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2?d1)/d1 is ?3×10?3 or more and 3×10?3 or less, and (d3?d1)/d1 is ?3×10?3 or more and 3×10?3 or less.
    Type: Application
    Filed: January 19, 2015
    Publication date: December 1, 2016
    Inventors: Katsushi Akita, Kei Fujii, Takashi Kyono, Koji Nishizuka, Kaoru Shibata
  • Publication number: 20160247951
    Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.
    Type: Application
    Filed: August 18, 2014
    Publication date: August 25, 2016
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Koji Nishizuka, Takashi Kyono, Kaoru Shibata, Katsushi Akita
  • Patent number: 9425348
    Abstract: In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×1017 atoms/cm3 or lower, and an angle between a normal axis of a primary surface of the semi-polar plane substrate and a c-axis of the semi-polar plane substrate is not lower than 45 degrees and not higher than 80 degrees or not lower than 100 degrees and not higher than 135 degrees in a waveguide axis direction of the group III nitride semiconductor device.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 23, 2016
    Assignees: Summitomo Electric Industries, Ltd., SONY CORPORATION
    Inventors: Nobuhiro Saga, Shinji Tokuyama, Kazuhide Sumiyoshi, Takashi Kyono, Koji Katayama, Tatsushi Hamaguchi, Katsunori Yanashima
  • Patent number: 9379523
    Abstract: A Group III nitride semiconductor device comprises: a Group III nitride semiconductor layer having a primary surface, inclined with respect to a c-plane of the Group III nitride semiconductor at an angle in a range of 50 degrees or more and 80 degrees or less, of a Group III nitride semiconductor; a p-type Group III nitride semiconductor laminate including first to third p-type Group III nitride semiconductor layers, the first to third p-type Group III nitride semiconductor layers being provided on the primary surface of the Group III nitride semiconductor layer, the first and third p-type Group III nitride semiconductor layers sandwiching the second p-type Group III nitride semiconductor layer such that the second p-type Group III nitride semiconductor layer incorporates strain; and an electrode provided on the p-type Group III nitride semiconductor laminate. The electrode is in contact with the first p-type Group III nitride semiconductor layer.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 28, 2016
    Assignees: Sumitomo Electric Industries, Ltd., SONY CORPORATION
    Inventors: Yohei Enya, Takashi Kyono, Masaki Ueno, Takao Nakamura, Takashi Matsuura, Tatsushi Hamaguchi, Yuji Furushima
  • Patent number: 9281427
    Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 8, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Kyono, Suguru Arikata, Katsushi Akita
  • Patent number: 9231375
    Abstract: A semiconductor device includes: a semiconductor substrate made of a hexagonal Group III nitride semiconductor and having a semi-polar plane; and an epitaxial layer formed on the semi-polar plane of the semiconductor substrate and including a first cladding layer of a first conductive type, a second cladding layer of a second conductive type, and a light-emitting layer formed between the first cladding layer and the second cladding layer, the first cladding layer being made of Inx1Aly1Ga1-x1-y1N, where x1>0 and y1>0, the second cladding layer being made of Inx2Aly2Ga1-x2-y2N, where0?x2?about 0.02 and about 0.03?y2?about 0.07.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: January 5, 2016
    Assignees: Sony Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Kunihiko Tasai, Hiroshi Nakajima, Noriyuki Futagawa, Katsunori Yanashima, Yohei Enya, Tetsuya Kumano, Takashi Kyono
  • Patent number: 9231370
    Abstract: A group III nitride semiconductor laser device includes a laser structure, an insulating layer, an electrode and dielectric multilayers. The laser structure includes a semiconductor region on a semi-polar primary surface of a hexagonal group III nitride semiconductor support base. The dielectric multilayers are on first and second end-faces for the laser cavity. The c-axis of the group III nitride tilts by an angle ALPHA from the normal axis of the primary surface in the waveguide axis direction from the first end-face to the second end-faces. A pad electrode has first to third portions provided on the first to third regions of the semiconductor regions, respectively. An ohmic electrode is in contact with the third region through an opening of the insulating layer. The first portion has a first arm, which extends to the first end-face edge. The third portion is away from the first end-face edge.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 5, 2016
    Assignees: Sumitomo Electric Industries, Ltd., SONY CORPORATION
    Inventors: Takamichi Sumitomo, Takashi Kyono, Masaki Ueno, Yusuke Yoshizumi, Yohei Enya, Masahiro Adachi, Shimpei Takagi, Katsunori Yanashima
  • Publication number: 20150372174
    Abstract: An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs1-aSba where the ratio a is 0 or more and 0.05 or less, a second component layer formed of GaSb, and a third component layer formed of InSbxAs1-x where the ratio x is more than 0 and less than 1. The third component layer is disposed so as to be in contact with one main surface of the second component layer. The other main surface of the second component layer is in contact with the first component layer within the unit structure. The third component layer has a thickness of 0.1 nm or more and 0.9 nm or less.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 24, 2015
    Inventors: Takashi KYONO, Suguru ARIKATA, Katsushi AKITA
  • Publication number: 20150255958
    Abstract: A Group III nitride semiconductor device comprises: a Group III nitride semiconductor layer having a primary surface, inclined with respect to a c-plane of the Group III nitride semiconductor at an angle in a range of 50 degrees or more and 80 degrees or less, of a Group III nitride semiconductor; a p-type Group III nitride semiconductor laminate including first to third p-type Group III nitride semiconductor layers, the first to third p-type Group III nitride semiconductor layers being provided on the primary surface of the Group III nitride semiconductor layer, the first and third p-type Group III nitride semiconductor layers sandwiching the second p-type Group III nitride semiconductor layer such that the second p-type Group III nitride semiconductor layer incorporates strain; and an electrode provided on the p-type Group III nitride semiconductor laminate. The electrode is in contact with the first p-type Group III nitride semiconductor layer.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 10, 2015
    Inventors: Yohei ENYA, Takashi KYONO, Masaki UENO, Takao NAKAMURA, Takashi MATSUURA, Tatsushi HAMAGUCHI, Yuji FURUSHIMA
  • Patent number: 9123843
    Abstract: A semiconductor device includes a semiconductor layer laminate in which a plurality of semiconductor layers are laminated, the semiconductor layer laminate including a light receiving layer, the light receiving layer being grown by a metal-organic vapor phase epitaxy method, the light receiving layer having a cutoff wavelength of more than or equal to 3 ?m and less than or equal to 8 ?m, the semiconductor device having a dark current density of less than or equal to 1×10?1 A/cm2 when a reverse bias voltage of 60 mV is applied at a temperature of ?140° C. Thereby, a semiconductor device which can receive light in a mid-infrared range and has a low dark current is provided.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 1, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Katsushi Akita, Kaoru Shibata, Koji Nishizuka, Kei Fujii
  • Publication number: 20150144876
    Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.
    Type: Application
    Filed: February 5, 2015
    Publication date: May 28, 2015
    Inventors: Takashi Kyono, Kei Fujii, Katsushi Akita
  • Publication number: 20150115222
    Abstract: A semiconductor device includes a semiconductor layer laminate in which a plurality of semiconductor layers are laminated, the semiconductor layer laminate including a light receiving layer, the light receiving layer being grown by a metal-organic vapor phase epitaxy method, the light receiving layer having a cutoff wavelength of more than or equal to 3 ?m and less than or equal to 8 ?m, the semiconductor device having a dark current density of less than or equal to 1×10?1 A/cm2 when a reverse bias voltage of 60 mV is applied at a temperature of ?140° C. Thereby, a semiconductor device which can receive light in a mid-infrared range and has a low dark current is provided.
    Type: Application
    Filed: September 22, 2014
    Publication date: April 30, 2015
    Inventors: Takashi KYONO, Katsushi AKITA, Kaoru SHIBATA, Koji NISHIZUKA, Kei FUJII
  • Publication number: 20150115312
    Abstract: In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×1017 atoms/cm3 or lower, and an angle between a normal axis of a primary surface of the semi-polar plane substrate and a c-axis of the semi-polar plane substrate is not lower than 45 degrees and not higher than 80 degrees or not lower than 100 degrees and not higher than 135 degrees in a waveguide axis direction of the group III nitride semiconductor device.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Inventors: Nobuhiro Saga, Shinji Tokuyama, Kazuhide Sumiyoshi, Takashi Kyono, Koji Katayama, Tatsushi Hamaguchi, Katsunori Yanashima
  • Publication number: 20150050768
    Abstract: A laser diode device includes: a semiconductor substrate including a semi-polar surface, the semiconductor substrate being formed of a hexagonal III-nitride semiconductor; an epitaxial layer including a light emitting layer, the epitaxial layer being formed on the semi-polar surface of the semiconductor substrate, and the epitaxial layer including a ridge section; a first electrode formed on a top surface of the ridge section; an insulating layer covering the epitaxial layer in an adjacent region of the ridge section and a side surface of the ridge section, the insulating layer covering part or all of side surfaces of the first electrode continuously from the epitaxial layer; a pad electrode formed to cover a top surface of the first electrode and the insulating layer, the pad electrode being electrically connected to the first electrode; and a second electrode formed on a surface, of the semiconductor substrate, opposite to the semi-polar surface.
    Type: Application
    Filed: September 26, 2014
    Publication date: February 19, 2015
    Inventors: Noriyuki FUTAGAWA, Hiroshi NAKAJIMA, Katsunori YANASHIMA, Takashi KYONO, Masahiro ADACHI