Abstract: An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.

Abstract: Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

Abstract: In order to provide a noise removal method for removing noise signals mixed into an image signal without deteriorating picture quality of the overall image, such zigzag noise signals that the difference between the output levels of two pixels adjacent to each other along a noise generation direction alternately takes positive and negative vales at least three times are detected from noise signals mixed into an image signal. Then, a specific pixel is noted among a plurality of pixels corresponding to the noise signals, for calculating a mean value of the output levels of the noise signals with reference to the specific pixel and correcting the output level of a noise signal corresponding to the said specific pixel with the said mean value.

Abstract: In a cooling structure of a cylinder block, a cooling medium is supplied into the cylinder block in which a water jacket continuously extends around a bore wall, so as to uniform the bore wall temperature. The cooling structure sets a cooling characteristic of the water jacket based on at least one of variation in the bore wall temperature in a direction perpendicular to the axis of the borehole and variation in the temperature of the cooling medium flowing around the bore wall. The structure improves the cylinder bore cooling efficiency or the cooling uniformity.

Abstract: Either the master address decode signal 4 generated by the master address decoder 3 or the reception interrupt factor vector decode signal 22 generated by the reception interrupt factor vector decoder 21 which decodes the reception interrupt factor vector 20, is select, ed by the decoder output select circuit 23 controlled by the interrupt vector register read signal 11, and the output from the decoder output select circuit 23 is given to each control register 5 as the multi function register select signal 24, and the AND signal of the multi function register select signal 24 obtained by the AND gate 110 and the interrupt vector register read signal 11, clears the interrupt request latch 6. During the time, by the interrupt vector register read signal 11, the bus cycle effective signal 9 to each control register 5 is masked.