Patents by Inventor Takashi Morie

Takashi Morie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8692701
    Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shoji Kawahito, Sung Wook Jung, Osamu Kobayashi, Yasuhide Shimizu, Takahiro Miki, Takashi Morie, Hirotomo Ishii
  • Publication number: 20140062750
    Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Takashi MORIE, Shiro SAKIYAMA, Naoshi YANAGISAWA, Toshiaki OZEKI, Takuji MIKI
  • Publication number: 20130285579
    Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: AKIRA KAWABE, KOUJI OKAMOTO, FUMIAKI SENOUE, HITOSHI KOBAYASHI, KIYOTAKA TANIMOTO, HIDEKI NISHINO, SHIRO SAKIYAMA, TAKASHI MORIE, AKIO YOKOYAMA
  • Publication number: 20130251206
    Abstract: In an object detection method and an object detector 10 using the method, HOG feature (A) of a target image is computed, and existence of a target object P in the image is judged based on HOG feature (B) pre-computed for a sample image 20 having the object P pictured therein. A classifier 18 to judge the existence of the object P in the image is constructed based on a feature pattern representing the existence of the object P obtained by calculating a plurality of the HOG features (B) having different bin numbers for each of a plurality of local areas (cells) 19 in the image 20. The existence of the object P in the image is judged by the classifier 18 based on a plurality of the HOG features (A) having different bin numbers computed for each of the local areas 19 in the image.
    Type: Application
    Filed: November 28, 2011
    Publication date: September 26, 2013
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Seiji Ishikawa, Joo Kooi Tan, Yuuki Nakashima, Takashi Morie
  • Publication number: 20130057418
    Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 7, 2013
    Inventors: Shoji KAWAHITO, Sung Wook JUNG, Osamu KOBAYASHI, Yasuhide SHIMIZU, Takahiro MIKI, Takashi MORIE, Hirotomo ISHII
  • Patent number: 8258990
    Abstract: An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n?1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n?1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: September 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama
  • Publication number: 20120112939
    Abstract: A digital correction circuit calculates AD conversion errors EA and EA? in AD conversion stages subsequent to a target stage of AD conversion. EA is an error between an AD conversion result when a digital output of the target stage is set to 0, and an AD conversion result when it is set to +1 in a state where a higher reference voltage is input to the target stage. EB is an error between an AD conversion result when the digital output is set to 0, and an AD conversion result when it is set to ?1 in a state where a lower reference voltage is input to the target stage. The digital correction circuit adds a correcting value of the target stage to the digital output. The correcting value is ?(EA+EB)/2 when the digital output is ?1, ?(EA?EB)/2 when it is 0, and +(EA+EB)/2 when it is +1.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Takuji MIKI, Takashi Morie
  • Patent number: 8130608
    Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 6, 2012
    Assignee: Panasonic Corporation
    Inventors: Akinori Matsumoto, Shiro Sakiyama, Shiro Dosho, Yusuke Tokunaga, Takashi Morie
  • Publication number: 20110291873
    Abstract: In a differential amplifier, input terminals to which a differential input is given are connected to gates of input transistors, respectively. One ends of capacitive devices are connected to sources of the input transistors, respectively. A switching section switches connection between the other ends of the capacitive devices and the input terminals according to a control clock at each phase.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 1, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiaki OZEKI, Takashi Morie
  • Publication number: 20110080821
    Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Akinori Matsumoto, Shiro Sakiyama, Shiro Dosho, Yusuke Tokunaga, Takashi Morie
  • Patent number: 7920002
    Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Akinori Matsumoto, Takashi Morie, Kazuaki Sogawa, Yukihiro Sasagawa, Masaya Sumita
  • Patent number: 7911369
    Abstract: A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Takashi Morie, Kazuo Matsukawa, Shiro Sakiyama, Shiro Dosho, Yusuke Tokunaga
  • Publication number: 20110050476
    Abstract: An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n?1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n?1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama
  • Patent number: 7855670
    Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa
  • Patent number: 7812637
    Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: October 12, 2010
    Assignee: Panasonic Cororation
    Inventors: Akinori Matsumoto, Shiro Sakiyama, Takashi Morie
  • Patent number: 7808307
    Abstract: A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Akinori Matsumoto, Takashi Morie, Masayoshi Kinoshita
  • Patent number: 7808295
    Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Akinori Matsumoto, Takashi Morie, Shiro Dosho, Yusuke Tokunaga
  • Patent number: 7773023
    Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa
  • Publication number: 20100182181
    Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Applicant: Panasonic Corporation
    Inventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa
  • Patent number: 7747668
    Abstract: A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: June 29, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Nomura, Takashi Morie, Keisuke Korekado