Patents by Inventor Takashi Nakabayashi

Takashi Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030205820
    Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
  • Patent number: 6621123
    Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: September 16, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nakabayashi, Chiaki Kudo
  • Patent number: 6492672
    Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: December 10, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
  • Publication number: 20020167977
    Abstract: A light generating module 1 comprises a housing 2, a semiconductor light-emitting device 4, a driving element 6, and a monitoring light-receiving device 8. The monitoring light-receiving device 8 is optically coupled with the semiconductor light-emitting device 4. The driving element 6 drives the semiconductor light-emitting device 4. The housing 2 contains the semiconductor light-emitting device 4, the driving element 6, and the monitoring light-receiving device 8. These elements 4, 6, and 8 are disposed sequentially along a predetermined axis. The driving element 6 is disposed between the semiconductor light-emitting device 4 and the monitoring light-receiving device 8. This configuration makes it possible to dispose the driving element 6 close to the semiconductor light-emitting device 4 so as to achieve a transmission rate of 10 Gbps without degrading the optical coupling between the semiconductor light-receiving device 8 and the semiconductor light-emitting device 4.
    Type: Application
    Filed: February 22, 2002
    Publication date: November 14, 2002
    Inventors: Takashi Nakabayashi, Atsushi Hamakawa
  • Publication number: 20020167017
    Abstract: A package 22 contains therein a semiconductor laser element 12 for emitting light and a semiconductor circuit element 14 for driving the semiconductor laser element 12 and is provided with an optical fiber supporting face 44 and an back face 46. The optical fiber supporting face 44 is provided for supporting an optical fiber 16 for transmitting the light from the semiconductor laser element 12, and the back face 46 is opposed to the optical fiber supporting face 44. The back face 46 has a lead pin 31 for feeding a positive-phase signal into the semiconductor circuit element 14 and a lead pin 32 for feeding a negative-phase signal into the semiconductor circuit element. The lead pins 31 and 32 penetrate through the back face 46.
    Type: Application
    Filed: March 11, 2002
    Publication date: November 14, 2002
    Inventors: Takashi Nakabayashi, Noriaki Kaida
  • Publication number: 20020024076
    Abstract: An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulating film. For example, a dummy gate line and a cylindrical wall formed thereon are provided as the etch stopper member. Either the dummy gate line or the cylindrical wall may be provided as the etch stopper member. The etch stopper member prevents the interlayer insulating film from being laterally etched at the boundary between a DRAM memory section and a logic section. This eliminates the need to provide an etching margin, allowing for reduction in the area of the DRAM memory section.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 28, 2002
    Inventor: Takashi Nakabayashi
  • Publication number: 20020014659
    Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a sidewall spacer is then formed at the lateral sides of the gate electrode on the semiconductor substrate. Epitaxial growth is conducted at a lower growth rate to form, at both lateral sides of the sidewall spacer on the semiconductor substrate, first semiconductor layers made of first single-crystal silicon films superior in crystallinity. Then, epitaxial growth is conducted at a higher growth rate to form, on the first semiconductor layers, second semiconductor layers made of single-crystal films or polycrystalline films, which are inferior in crystallinity, or amorphous films. The upper areas of the first semiconductor layers and the whole areas of the second semiconductor layers are doped with impurity, thus forming impurity diffusion layers respectively serving as a source and a drain.
    Type: Application
    Filed: October 3, 2001
    Publication date: February 7, 2002
    Inventor: Takashi Nakabayashi
  • Publication number: 20010054741
    Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.
    Type: Application
    Filed: July 11, 2001
    Publication date: December 27, 2001
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.,LTD.
    Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
  • Patent number: 6319782
    Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a sidewall spacer is then formed at the lateral sides of the gate electrode on the semiconductor substrate. Epitaxial growth is conducted at a lower growth rate to form, at both lateral sides of the sidewall spacer on the semiconductor substrate, first semiconductor layers made of first single-crystal silicon films superior in crystallinity. Then, epitaxial growth is conducted at a higher growth rate to form, on the first semiconductor layers, second semiconductor layers made of single-crystal films or polycrystalline films, which are inferior in crystallinity, or amorphous films. The upper areas of the first semiconductor layers and the whole areas of the second semiconductor layers are doped with impurity,thus forming impurity diffusion layers respectively serving as a source and a drain.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: November 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takashi Nakabayashi
  • Patent number: 6281562
    Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: August 28, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
  • Patent number: 6280888
    Abstract: Transmitting portions of a phase-shifting mask include plural first transmitting areas periodically arranged along a first direction and a second direction and a second transmitting area provided in an area surrounded with adjacent four first transmitting areas among the plural first transmitting areas. The first transmitting areas are formed by recessing a board so that a phase difference of substantially 180 degrees in exposure light can be caused between adjacent first transmitting areas. A phase difference of substantially 90 degrees in the exposure light is caused between the second transmitting area and the surrounding first transmitting areas. Thus, isolated patterns arranged at high density can be formed correspondingly to the first transmitting areas and the second transmitting area.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: August 28, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Takashi Nakabayashi, Koji Matsuoka
  • Patent number: 6143626
    Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Takashi Nakabayashi
  • Patent number: 6124160
    Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: September 26, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
  • Patent number: 6114095
    Abstract: Transmitting portions of a phase-shifting mask include plural first transmitting areas periodically arranged along a first direction and a second direction and a second transmitting area provided in an area surrounded with adjacent four first transmitting areas among the plural first transmitting areas. The first transmitting areas are formed by recessing a board so that a phase difference of substantially 180 degrees in exposure light can be caused between adjacent first transmitting areas. A phase difference of substantially 90 degrees in the exposure light is caused between the second transmitting area and the surrounding first transmitting areas. Thus, isolated patterns arranged at high density can be formed correspondingly to the first transmitting areas and the second transmitting area.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: September 5, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Takashi Nakabayashi, Koji Matsuoka
  • Patent number: 6093592
    Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: July 25, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nakabayashi, Chiaki Kudo
  • Patent number: 5960300
    Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: September 28, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Takashi Nakabayashi
  • Patent number: 5946563
    Abstract: There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takashi Nakabayashi, Minoru Fujii
  • Patent number: 5925912
    Abstract: In an active area on a semiconductor substrate is formed a MOS transistor including a gate insulating film, gate electrode, an insulating film formed on the entire surface of the substrate, a conductive side wall formed on the side surfaces of the gate electrode with the insulating film interposed therebetween, low concentration source/drain regions and high concentration source/drain regions. The high concentration drain region and the conductive side wall are electrically conducting to each other via a second interconnection within a second contact hole. In the usage of the MOS transistor, the conductive side wall is at the same potential as the drain voltage, thereby suppressing the degradation due to a hot carrier. In addition, since there is no need to provide an alignment margin between the second contact hole and the gate electrode, the area of the drain region is decreased.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: July 20, 1999
    Assignee: Matsushita Electric Industrial Co.,Ltd.
    Inventors: Masatoshi Arai, Takashi Nakabayashi
  • Patent number: 5903031
    Abstract: In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: May 11, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takayuki Yamada, Takashi Nakabayashi, Masatoshi Arai, Toshiki Yabu, Koji Eriguchi
  • Patent number: 5879983
    Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: March 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada