Patents by Inventor Takashi Nakagawa

Takashi Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10263119
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Publication number: 20190096206
    Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.
    Type: Application
    Filed: March 9, 2017
    Publication date: March 28, 2019
    Inventors: Takashi NAKAGAWA, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA
  • Publication number: 20190074278
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 7, 2019
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
  • Patent number: 10183007
    Abstract: The present invention relates to a composition containing as its main component proanthocyanidin oligomer to which a substance having a phloroglucinol ring structure or resorcinol ring structure has been bonded and reduced in the molecular weight, which is obtained by heating plant materials containing proanthocyanidin polymer or extract thereof with a substance having a phloroglucinol ring structure or resorcinol ring structure in an acidic aqueous solution, production method thereof, and uses of the composition in health products and pharmaceutical products. According to the invention, proanthocyanidin oligomer having physiological activity, to which a substance having a phloroglucinol ring structure or resorcinol ring structure has been bonded and reduced in the molecular weight to such a level that the oligomer can be absorbed into living body, which has been conventionally difficult to obtain at high yield from plant raw materials, can be produced efficiently and easily.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 22, 2019
    Assignees: Usien Pharmaceutical Co., Ltd., Amino Up Chemical Co., Ltd., Nagasaki University
    Inventors: Takashi Tanaka, Gen-ichiro Nonaka, Isao Kohno, Hajime Fujii, Takashi Nakagawa, Hiroshi Nishioka
  • Publication number: 20190010149
    Abstract: The present invention relates to a composition comprising N-[4-[4-(1,2-benzisothiazol-3-yl)-1-piperazinyl]-(2R,3R)-2,3-tetramethylene-butyl]-(1?R,2?S,3?R,4?S)-2,3-bicyclo[2,2,1]heptanedicarboximide or a pharmaceutically acceptable acid addition salt thereof. In detail, the composition relates to a sustained release formulation for injection which maintains an effective blood level of the above-mentioned compound.
    Type: Application
    Filed: September 12, 2018
    Publication date: January 10, 2019
    Applicant: SUMITOMO DAINIPPON PHARMA CO., LTD.
    Inventors: Takashi NAKAGAWA, Norimasa Koseki
  • Patent number: 10152936
    Abstract: A novel circuit, a novel display portion, a novel display system, or the like is provided. A circuit, a display portion, a display system, or the like which has low power consumption is provided. A plurality kinds of video signals are generated by division of input data and supplied to different pixel groups. Thus, for example, the plurality of video signals can be supplied individually, and the operation states of a plurality of driver circuits can be controlled individually, leading to fine-grained operation with low power consumption. Accordingly, a decoder, a display portion, or a display system having low power consumption can be provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Seiichi Yoneda
  • Patent number: 10128249
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
  • Patent number: 10090322
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Toshiyuki Kikuchi, Atsushi Moriya, Masanori Nakayama, Takashi Nakagawa
  • Publication number: 20180265471
    Abstract: The present invention provides a novel compound having an excellent antitumor effect, stability and metabolic stability. The compound of the present invention is represented by the following general formula (1) wherein R1 represents a halogen atom, an aryl group, an aryloxy group or a lower alkyl group optionally substituted with one or more halogen atoms; R2 represents a hydrogen atom, a halogen atom, a lower alkyl group or a lower alkoxy group; and; m represents an integer of 1 to 3; provided that when m represents 2 or 3, R1s are the same or different.
    Type: Application
    Filed: May 2, 2018
    Publication date: September 20, 2018
    Applicant: OTSUKA PHARMACEUTICAL CO., LTD.
    Inventors: Takashi NAKAGAWA, Makoto SAKAMOTO, Kazuya YAMAGUCHI, Yuki TERAUCHI, Masamichi SHIRAKURA, Yasuo HARADA, Yutaka KOJIMA, Takumi SUMIDA
  • Publication number: 20180269762
    Abstract: A rotor in one embodiment includes an annular rotor main unit and a fitting portion that extends inward or outward one of an inner circumference and an outer circumference of the rotor main unit to be connected with a rotary shaft. The fitting portion is formed at a position at which a centerline of the fitting portion is offset in parallel with respect to a normal line that is associated with a tangent line of the one of the inner circumference and the outer circumference.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 20, 2018
    Inventors: Hiroshi ABE, Takashi NAKAGAWA
  • Publication number: 20180197877
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 12, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Toshiyuki KIKUCHI, Atsushi MORIYA, Masanori NAKAYAMA, Takashi NAKAGAWA
  • Publication number: 20180145333
    Abstract: Provided is an electrode mixture layer capable of reducing internal resistance by use of a carbon nanotube molding. The electrode mixture layer includes an active material and a conductor of carbon nanotubes in close contact with the surface of the active material, and the number density of the carbon nanotubes is 4 tubes/?m or more. The number density is defined as a value obtained by providing measurement lines on a scanning electron microscope image of a surface of the electrode mixture layer at 0.3 ?m intervals both longitudinally and laterally, measuring the total number of the carbon nanotubes being in close contact with the surface of the active material and intersecting the measurement lines, and dividing the total number of the carbon nanotubes by the total length of the measurement lines on the active material surface.
    Type: Application
    Filed: October 12, 2017
    Publication date: May 24, 2018
    Inventors: Toshio TOKUNE, Takuya NISHINUMA, Takahiro KOMORI, Kenshi INOUE, Kiyoshi TANAAMI, Takashi NAKAGAWA
  • Patent number: 9979386
    Abstract: A semiconductor device that suppresses operation delay due to stop and restart of the supply of a power supply potential is provided. A potential corresponding to data held while power supply potential is continuously supplied is backed up in a node connected to a capacitor while the supply of the power supply potential is stopped. Then, by utilizing change in resistance of a channel in a transistor whose gate is the node, the data is restored with restart of the supply of the power supply potential. Note that by supplying a high potential to the node before the data back up, high-speed and accurate data back up is possible.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Takeshi Aoki, Takashi Nakagawa
  • Publication number: 20180090616
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 29, 2018
    Inventors: Takashi NAKAGAWA, Yoshiyuki KUROKAWA, Munehiro KOZUMA
  • Patent number: 9925704
    Abstract: An in-mold molding method of the present invention is a method including: placing an in-mold transfer film in the cavity of an injection molding mold, the in-mold transfer film having a hard coating layer and a transfer section of a printed layer; and peeling, from the base material film of the in-mold transfer film, the transfer section transferred to a molding resin when a molding molded by injecting the molding resin into the cavity is removed by mold opening. The hard coating layer is ruptured in a mold opening process while the in-mold transfer film has a necessary elongation of A % on the side of the molding and the hard coating layer has a rupture elongation of at least A %+2% and less than A %+40% on the side of the molding. With this configuration, the in-mold transfer film can be stably peeled during in-mold molding.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Nakagawa, Mitsuhiro Yoshinaga
  • Patent number: 9910084
    Abstract: A flexible circuit board inspecting apparatus for conducting an inspection on a flexible circuit board includes a transport path and an inspection part mechanism. The transport path is configured to successively transport the flexible circuit board having a plurality of unit circuit boards arranged thereon. The inspection part mechanism is configured to bring and distance a jig for inspecting the flexible circuit board transported on the transport path close to and from the flexible circuit board. The transport path includes a longitudinal transport portion for transporting the flexible circuit board in a downward vertical direction. The inspection part mechanism moves the jig in a direction perpendicular to the flexible circuit board transported on the longitudinal transport portion to bring and distance the jig close to and from the flexible circuit board.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 6, 2018
    Assignee: NIDEC-READ CORPORATION
    Inventors: Takashi Nakagawa, Toshihide Matsukawa, Osamu Hikita, Michio Kaida
  • Publication number: 20180033696
    Abstract: A novel semiconductor device, a semiconductor device with low power consumption, a semiconductor device capable of displaying a high-quality image, or a semiconductor device with a small area is provided. The semiconductor device includes an image processing portion and a driver circuit. The image processing portion includes a processor and a correction circuit. The correction circuit includes a PLD. The correction circuit is capable of correcting data input from the processor using the PLD. The processor is capable of outputting data corrected by the correction circuit to the driver circuit as a video signal. The PLD is capable of executing first gamma correction by input of first configuration data. The PLD is capable of executing second gamma correction by input of second configuration data. The content of the first gamma correction is different from that of the second gamma correction.
    Type: Application
    Filed: July 19, 2017
    Publication date: February 1, 2018
    Inventors: Takashi NAKAGAWA, Yuki OKAMOTO
  • Patent number: 9877652
    Abstract: A measurement device includes: a measurement portion that acquires measurement data; a setting portion that specifies an external device as a transmission destination of the measurement data based on a signal transmitted from the external device, and allows communication with the external device without receiving input of authentication information; and a transmission and reception portion that transmits measurement data to the external device. The setting portion causes the transmission and reception portion to transmit identification information of the measurement device to the external device, and further to transmit confirmation information thereto in addition to the identification information. The confirmation information is used by the external device to decide whether or not the external device can handle the measurement data transmitted from the measurement device.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 30, 2018
    Assignee: ARKRAY, Inc.
    Inventor: Takashi Nakagawa
  • Patent number: 9870827
    Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Hiroki Inoue, Fumika Akasawa, Yoshiyuki Kurokawa
  • Publication number: 20170347465
    Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m
    Type: Application
    Filed: August 15, 2017
    Publication date: November 30, 2017
    Inventors: Kenji Iida, Takashi Nakagawa, Seigo Yamawaki, Yasuhiro Karahashi, Junichi Kanai, Koji Komemura