Patents by Inventor Takashi Noma
Takashi Noma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040262732Abstract: A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.Type: ApplicationFiled: April 21, 2004Publication date: December 30, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Akira Suzuki, Hiroyuki Shinogi
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Publication number: 20040235270Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.Type: ApplicationFiled: June 28, 2004Publication date: November 25, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
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Publication number: 20040229445Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.Type: ApplicationFiled: February 24, 2004Publication date: November 18, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
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Publication number: 20040161920Abstract: The invention is directed to improving of a yield and reliability of a BGA type semiconductor device having ball-shaped conductive terminals. A semiconductor wafer having warped portions is supported by a plurality of pins, being spaced from a heated stage. The semiconductor wafer is heated as a whole by uniformly irradiating thermal radiation thereto by using IR heaters disposed on an upper part of the semiconductor wafer and side heaters facing to lateral surfaces of the semiconductor wafer. This enables uniform reflowing of the conductive terminals provided on the semiconductor wafer, and makes each of the conductive terminals form a uniform shape.Type: ApplicationFiled: December 12, 2003Publication date: August 19, 2004Applicant: Sanyo Electric Co., Ltd.Inventor: Takashi Noma
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Publication number: 20040137723Abstract: A first glass substrate is bonded through a resin to a top surface of a semiconductor wafer on which a first wiring is formed. A second glass substrate is bonded to a back surface of the semiconductor wafer through a resin. A V-shaped groove is formed by notching from a surface of the second glass substrate through a part of the first glass substrate. A second wiring connected with the first wiring and extending to the surface of the second glass substrate is formed. A protection film composed of an organic resin and a photoresist layer to provide the protection film with an opening are formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the second glass substrate by spray coating.Type: ApplicationFiled: October 30, 2003Publication date: July 15, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Akira Suzuki, Yoshinori Seki, Koichi Kuhara, Yukihiro Takao, Hiroshi Yamada
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Publication number: 20040121562Abstract: A semiconductor device manufacturing method comprises a step of forming a laminated structure by adhering, on a semiconductor substrate including a plurality of integrated circuits, a carrier member covering a region in which the plurality of integrated circuits are formed, with an insulating resin interposed between the semiconductor substrate and the carrier member, a step of cutting a notch into the laminated structure so as to cut the semiconductor substrate together with the insulating resin while allowing at least a portion of the carrier member to remain uncut, and a dicing step for dividing the laminated structure by cutting the carrier member. The notch cutting step is performed while cooling a dicing saw used to cut the semiconductor substrate.Type: ApplicationFiled: November 14, 2003Publication date: June 24, 2004Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Motoaki Wakui, Kaoru Sasaki, Kenji Imai, Hiroyuki Shinogi, Takashi Noma
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Publication number: 20040063268Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.Type: ApplicationFiled: June 17, 2003Publication date: April 1, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao
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Publication number: 20040002276Abstract: To reuse glass used in a flat panel display, processing suitable for global environment such as processing of separating a lead component must be realized. A disassembly processing method for a flat panel display having a structure in which a face plate and rear plate mainly containing glass are airtightly joined via a frame with frit glass is characterized by including the step of separating the face plate and rear plate joined with the frit glass. The separation step is characterized by separating the face plate and rear plate by cutting, dissolution, or melting.Type: ApplicationFiled: June 17, 2003Publication date: January 1, 2004Applicant: CANON KABUSHIKI KAISHAInventors: Takashi Noma, Toyoko Kobayashi, Taiko Motoi, Hiromitsu Takase, Naoko Miura, Shin Kobayashi
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Publication number: 20030230805Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.Type: ApplicationFiled: April 23, 2003Publication date: December 18, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
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Patent number: 6654221Abstract: Current flowing through a cold cathode tube is detected and converted to a voltage with a resistor, and is fed to a tube current control circuit. The tube current control circuit drives a drive circuit to control a voltage applied to a piezoelectric transformer. Current from a constant-current source is used to charge a fault protection capacitor. A transistor is allowed to conduct while current flows through the cold cathode tube so that a voltage is developed in a resistor, and thereby, an electric charge is prevented from being stored in the fault protection capacitor, thereby stopping the operation of a fault protection circuit.Type: GrantFiled: August 7, 2001Date of Patent: November 25, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Takashi Noma, Yasuyuki Morishima
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Patent number: 6632113Abstract: To reuse glass used in a flat panel display, processing suitable for global environment such as processing of separating a lead component must be realized. A disassembly processing method for a flat panel display having a structure in which a face plate and rear plate mainly containing glass are airtightly joined via a frame with frit glass is characterized by including the step of separating the face plate and rear plate joined with the frit glass. The separation step is characterized by separating the face plate and rear plate by cutting, dissolution, or melting.Type: GrantFiled: November 28, 2000Date of Patent: October 14, 2003Assignee: Canon Kabushiki KaishaInventors: Takashi Noma, Toyoko Kobayashi, Taiko Motoi, Hiromitsu Takase, Naoko Miura, Shin Kobayashi
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Patent number: 6593950Abstract: An electron-emitting device having an electron-emitting region between electrodes on a substrate where the electron-emitting region contains fine particles dispersed therein at an areal occupation ratio of the fine particles ranging from 20% to 75% of the electron-emitting region is disclosed. The other electron-emitting device where the electron-emitting region contains fine particles being arranged at gaps of from 5 Å to 100 Å and having average particle diameter of from 5 Å to 1000 Å is also disclosed. Electron beam-generating apparatus and image-forming apparatus comprise one of the electron-emitting regions and a modulation means for modulating the electron beams emitted from the electron-emitting devices in accordance with information signals.Type: GrantFiled: April 6, 1995Date of Patent: July 15, 2003Assignee: Canon Kabushiki KaishaInventors: Ichiro Nomura, Hidetoshi Suzuki, Takashi Noma, Yoshikazu Banno, Rie Ueno, Naoto Nakamura
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Publication number: 20020127386Abstract: A method for manufacturing a porous structured material comprises the steps of: preparing a reactant solution that contains a metal compound and a surfactant, coating a substrate with the reactant solution, and holding the substrate in an atmosphere containing water vapor. In a thin film of an oxide having a porous structure, a surfactant is retained in the pores, and the pore walls contain tin oxide crystals.Type: ApplicationFiled: February 4, 2002Publication date: September 12, 2002Inventors: Miki Ogawa, Takashi Noma
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Patent number: 6437424Abstract: A barrier film of a SiON film is formed below an interlayer insulating film which is a single layer film or laminated film of an TEOS film or SOG film covering a floating gate 4 and control gate 6. The SiON film which is good in moisture blocking but poor in coverage is covered with another TEOS film which is better in coverage than the SiON film, thereby improving the barrier property of the barrier film. Such a configuration prevents moisture or H atoms contained in the TEOS film or SOG film from being diffused and trapped by the tunneling oxide film 3, thereby improving the trap-up rate and hence endurance characteristic and extending the operation life of a memory cell.Type: GrantFiled: February 16, 2000Date of Patent: August 20, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Masaji Hara, Kimihide Saito, Ryo Kawai, Yoichi Kanuma, Kazuo Okada
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Publication number: 20020101696Abstract: Current flowing through a cold cathode tube is detected and converted to a voltage with a resistor, and is fed to a tube current control circuit. The tube current control circuit drives a drive circuit to control a voltage applied to a piezoelectric transformer. Current from a constant-current source is used to charge a fault protection capacitor. A transistor is allowed to conduct while current flows through the cold cathode tube so that a voltage is developed in a resistor, and thereby, an electric charge is prevented from being stored in the fault protection capacitor, thereby stopping the operation of a fault protection circuit.Type: ApplicationFiled: August 7, 2001Publication date: August 1, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Takashi Noma, Yasuyuki Morishima
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Publication number: 20020041294Abstract: An electron-emitting device having an electron-emitting region between electrodes on a substrate where the electron-emitting region contains fine particles dispersed therein at an areal occupation ratio of the fine particles ranging from 20% to 75% of the electron-emitting region is disclosed. The other electron-emitting device where the electron-emitting region contains fine particles being arranged at gaps of from 5 Å to 100 Å and having average particle diameter of from 5 Å to 1000 Å is also disclosed. Electron beam-generating apparatus and image-forming apparatus comprise one of the electron-emitting regions and a modulation means for modulating the electron beams emitted from the electron-emitting devices in accordance with information signals.Type: ApplicationFiled: April 6, 1995Publication date: April 11, 2002Inventors: ICHIRO NOMURA, HIDETOSHI SUZUKI, TAKASHI NOMA, YOSHIKAZU BANNO, RIE UENO, NAOTO NAKAMURA
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Patent number: 6320301Abstract: A piezoelectric-transformer inverter includes a piezoelectric transformer for supplying a transformed voltage to a load connected to a secondary electrode thereof. A first coil and a first transistor are connected to one primary electrode of the piezoelectric transformer, and a second coil and a second transistor are connected to the other primary electrode of the piezoelectric transformer. The first and second transistors are alternately turned on and off such that the phase of the voltage applied between the primary electrodes is reversed cyclically. The operation frequency is controlled such that an AC current flowing through the load is maintained at a predetermined level. The piezoelectric transformer has a piezoelectric substrate. In a first half region of the piezoelectric substrate, a plurality of electrode films are layered in order to form the primary electrodes. The secondary electrode is formed on an end surface of the piezoelectric substrate opposite to the primary electrodes.Type: GrantFiled: April 14, 1999Date of Patent: November 20, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Takashi Noma, Ken Takakura, Yasuyuki Morishima
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Patent number: 6281814Abstract: A peak detecting section 121 detects the maximum values (peaks) of frequency distributions, at intervals of unit times, from the wavelet intensity signal output from an intensity computing section 113. More specifically, giving attention to frequency distributions of the wavelet intensity signal as the transform result obtained by a signal converting section 110 at predetermined time intervals, the peak detecting section 121 detects the peaks (maximum values) of the frequency intensity distributions at intervals of unit times (predetermined time intervals). Changes in various frequency features over time which are contained in the time-series signal obtained by a wavelet transform of the time-series signal can be quantitatively grasped more accurately.Type: GrantFiled: February 1, 2000Date of Patent: August 28, 2001Assignee: Yamatake CorporationInventors: Hideki Sasaoka, Hirohiko Kazato, Takashi Noma
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Patent number: 6229720Abstract: A piezoelectric transformer inverter can suppress ripples generated by the oscillations of a transformer, and can reduce the possibility of occurrence of beats in the inverter. In this piezoelectric transformer inverter, a switching element is disposed at a stage before an inverter circuit driving a discharge tube, and the switching element is switched on and off by switching signals from a chopper-duty control unit. Then, an input voltage is converted into a rectangular-wave voltage having a chopper circuit frequency to be supplied to the inverter circuit, and a frequency of n times a driving frequency of the inverter circuit and a chopper frequency of the chopper circuit are set in such a manner that these two frequencies are not close to each other.Type: GrantFiled: March 27, 2000Date of Patent: May 8, 2001Assignee: Murata Manufacturing Co. Ltd.Inventors: Takashi Noma, Yasuyuki Morishima
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Patent number: 6184631Abstract: A piezoelectric inverter is disclosed. In the piezoelectric inverter, an input voltage controller, having a switching transistor and a current circulatingelement, converts an input voltage into a rectangular pulse alternating-current voltage. A piezoelectric transformer driver, having an inductive element, outputs an alternating-current voltage having a substantially constant frequency lower than the frequency of the alternating-current voltage output from the input voltage controller. A load current detect or detects a load current flowing through a discharge tube connected to a piezoelectric transformer. A duty factor controller controls the duty factor of the rectangular pulse of the input voltage controller in response to the output of the load current detector so that the load current coincides with a substantially constant target current value. The piezoelectric inverter thus controls the mean voltage of the alternating-current voltage applied to the piezoelectric transformer.Type: GrantFiled: March 16, 2000Date of Patent: February 6, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Takashi Noma, Yasuyuki Morishima