Patents by Inventor Takashi Noma

Takashi Noma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7362595
    Abstract: A DC-DC converter includes a regeneration preventing circuit to bring a synchronous rectifying switching element to an OFF-state when an output of an error amplifier is lower than a lower-limit potential of a triangular-wave signal, that is, when the output of the error amplifier deviates from a voltage range of the triangular-wave signal in a side (direction), which would cause a smaller ON duty ratio of a main switching element. This configuration prevents a rise of voltage in an input side due to a regenerative operation at startup when a pre-bias voltage exists. Also, the configuration prevents fluctuations of an output voltage at a sudden change of a load current and a drop of the output voltage at transition from a soft start state to a normal operation state when the load current is small.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: April 22, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Noma
  • Patent number: 7312521
    Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: December 25, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
  • Patent number: 7312107
    Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 25, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
  • Patent number: 7304463
    Abstract: A DC-DC converter includes an Nch FET1 which is series connected between an input terminal and an output terminal, and an Nch FET2 which is connected between the output terminal side of the Nch FET1 and a ground terminal. On the output terminal side of the circuits, a smoothing circuit and a comparator circuit are connected. The output side of the comparator circuit is connected to an on-time limiter circuit, and the on-time limiter circuit is connected to an H/S driver circuit for controlling the Nch FET1 through an inverter and directly connected to an L/S driver circuit for controlling the Nch FET2. Here, when a switching control signal for turning on the Nch FET1 is input to the on-time limiter circuit from the comparator, the on-time limiter circuit detects a time in the on state and outputs a signal by which the Nch FET1 is temporarily off controlled.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: December 4, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Noma
  • Patent number: 7271466
    Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: September 18, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
  • Publication number: 20070210437
    Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Shigeki Otsuka, Yuichi Morita, Kazuo Okada, Hiroshi Yamada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Publication number: 20070195565
    Abstract: A DC-DC converter includes a regeneration preventing circuit to bring a synchronous rectifying switching element to an OFF-state when an output of an error amplifier is lower than a lower-limit potential of a triangular-wave signal, that is, when the output of the error amplifier deviates from a voltage range of the triangular-wave signal in a side (direction), which would cause a smaller ON duty ratio of a main switching element. This configuration prevents a rise of voltage in an input side due to a regenerative operation at startup when a pre-bias voltage exists. Also, the configuration prevents fluctuations of an output voltage at a sudden change of a load current and a drop of the output voltage at transition from a soft start state to a normal operation state when the load current is small.
    Type: Application
    Filed: December 21, 2006
    Publication date: August 23, 2007
    Inventor: Takashi Noma
  • Patent number: 7256073
    Abstract: A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: August 14, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Akira Suzuki, Hiroyuki Shinogi
  • Publication number: 20070164719
    Abstract: A ripple converter includes a transistor for switching an input direct-current voltage, a choke coil and a smoothing capacitor for smoothing the switched direct-current voltage, a flywheel diode for causing a current to flow through the choke coil when the transistor is turned off, and a comparing unit for controlling the ON/OFF of the transistor according to ripple in an output voltage. In the ripple converter, a waveform converter is provided on a connecting path between an output terminal and a non-inverting input terminal of a comparator in the comparing unit. A result of converting the waveform of the output voltage is compared with a reference voltage, and a result of the comparison is fed back to the transistor.
    Type: Application
    Filed: March 29, 2007
    Publication date: July 19, 2007
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi NOMA, Hiroshi TAKEMURA
  • Publication number: 20070166955
    Abstract: The invention provides a package type semiconductor device and a method of manufacturing the same where reliability and yield are enhanced without making a manufacturing process complex. A resin layer and a supporting body are formed on a front surface of a semiconductor substrate formed with a pad electrode. Then, the resin layer and the supporting body are removed by etching so as to expose the pad electrode. By this etching, the supporting body in two conductive terminal formation regions facing each other over a dicing line and the supporting body in a region connecting with these regions therebetween are simultaneously removed to form an opening, as shown in FIG. 3C. Then, a metal layer is formed on the pad electrode exposed in the opening, and a conductive terminal is further formed thereon. Lastly, dicing is performed along the dicing line to separate the semiconductor substrate in individual semiconductor dies.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 19, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Takashi Noma
  • Publication number: 20070145420
    Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazuo Okada, Katsuhiko Kitagawa, Takashi Noma, Shigeki Otsuka, Hiroshi Yamada, Shinzo Ishibe, Yuichi Morita, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Publication number: 20070145590
    Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takashi Noma, Kazuo Okada, Shinzo Ishibe, Katsuhiko Kitagawa, Yuichi Morita, Shigeki Otsuka, Hiroshi Yamada, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Patent number: 7233135
    Abstract: A ripple converter includes a transistor for switching an input direct-current voltage, a choke coil and a smoothing capacitor for smoothing the switched direct-current voltage, a flywheel diode for causing a current to flow through the choke coil when the transistor is turned off, and a comparing unit for controlling the ON/OFF of the transistor according to ripple in an output voltage. In the ripple converter, a waveform converter is provided on a connecting path between an output terminal and a non-inverting input terminal of a comparator in the comparing unit. A result of converting the waveform of the output voltage is compared with a reference voltage, and a result of the comparison is fed back to the transistor.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: June 19, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Noma, Hiroshi Takemura
  • Patent number: 7208340
    Abstract: The invention is directed to improving of a yield and reliability of a BGA type semiconductor device having ball-shaped conductive terminals. A semiconductor wafer having warped portions is supported by a plurality of pins, being spaced from a heated stage. The semiconductor wafer is heated as a whole by uniformly irradiating thermal radiation thereto by using IR heaters disposed on an upper part of the semiconductor wafer and side heaters facing to lateral surfaces of the semiconductor wafer. This enables uniform reflowing of the conductive terminals provided on the semiconductor wafer, and makes each of the conductive terminals form a uniform shape.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 24, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takashi Noma
  • Publication number: 20070075425
    Abstract: The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 5, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yuichi Morita, Shinzo Ishibe, Takashi Noma, Hisao Otsuka, Yukihiro Takao, Hiroshi Kanamori
  • Patent number: 7199561
    Abstract: In a converter device, an N-type FET is connected in series between an input terminal and an output terminal and an N-type FET is connected between the side of the output terminal of the N-type FET1 and a ground terminal. A smoothing circuit and a comparator circuit are connected to the side of the output terminal of the circuits. The output side of the comparator circuit is connected to an H/S driver circuit controlling the N-type FET1 through an inverter and directly connected to an L/S driver circuit controlling the N-type FET2. A reference voltage correction circuit is included in the comparator circuit, and the comparator circuit outputs an appropriate switching control signal by comparing a correction reference voltage, obtained through comparison of a divider voltage in accordance with the time average value of an output voltage with a reference voltage, with the divider voltage.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: April 3, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Noma
  • Publication number: 20070023289
    Abstract: A novel structure is provided in which mesopores are oriented. Further a mesoporous film is provided which has two-branched diffraction peaks at intervals or 180° according to in-plane X-ray diffraction.
    Type: Application
    Filed: May 22, 2006
    Publication date: February 1, 2007
    Applicant: Canon Kabushiki Kaisha
    Inventors: Hirokatsu Miyata, Masatoshi Watanabe, Takashi Noma, Kazuyuki Kuroda, Takashi Suzuki, Ayumu Fukuoka
  • Publication number: 20070026639
    Abstract: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.
    Type: Application
    Filed: July 19, 2006
    Publication date: February 1, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Akira Suzuki, Yoshinori Seki, Koichi Kuhara, Yukihiro Takao, Hiroshi Yamada
  • Publication number: 20070018263
    Abstract: The invention is directed to enhancement of performance of a back surface incident type semiconductor device having a light receiving element and a manufacturing method thereof without increasing a manufacturing cost. A supporting body is attached to a front surface of a semiconductor substrate formed with a light receiving element and its pad electrode. Then, the supporting body is etched to form a via hole penetrating the supporting body and exposing the pad electrode. Then, a wiring connected to the pad electrode and extending onto a front surface of the supporting body through the via hole is formed. Lastly, the semiconductor substrate is separated into a plurality of semiconductor dies by dicing. The semiconductor device is mounted so that the supporting body faces a circuit board.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 25, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Takashi Noma
  • Publication number: 20070013353
    Abstract: In a converter device, an N-type FET is connected in series between an input terminal and an output terminal and an N-type FET is connected between the side of the output terminal of the N-type FET, and a ground terminal. A smoothing circuit and a comparator circuit are connected to the side of the output terminal of the circuits. The output side of the comparator circuit is connected to an H/S driver circuit controlling the N-type FET1 through an inverter and directly connected to an L/S driver circuit controlling the N-type FET2. A reference voltage correction circuit is included in the comparator circuit, and the comparator circuit outputs an appropriate switching control signal by comparing a correction reference voltage, obtained through comparison of a divider voltage in accordance with the time average value of an output voltage with a reference voltage, with the divider voltage.
    Type: Application
    Filed: April 27, 2005
    Publication date: January 18, 2007
    Inventor: Takashi Noma