Abstract: A motor includes: a central shaft; a stator extending in an axial direction around the central shaft; a rotor facing an outer side in a radial direction of the stator and configured to rotate around the central shaft; a substrate located on one side in the axial direction with respect to the rotor and on which a rotation position detection circuit detecting a rotation position of the rotor is mounted; and a case located on one side in the axial direction with respect to the substrate and supporting the stator. The stator includes a restricting portion restricting a position in a circumferential direction of the substrate. The case includes a fixing portion fixing the substrate. The substrate includes a restricted portion whose position in the circumferential direction is restricted by the restricting portion, and a fixed portion fixed to the fixing portion.

Abstract: There is provided a method for manufacturing an electrical wire. The electrical wire includes a rod-like conductor having a shape corresponding to a predetermined wiring route and also having rigidity to enable the rod-like conductor to maintain the shape, and an insulation sheath covering the rod-like conductor. The method includes: preparing a plurality of rod-like preliminary conductors having the rigidity so as to correspond to a plurality of sub routes into which the wiring route is divided; processing at least one of the plurality of preliminary conductors into a shape conforming to the corresponding sub routes; connecting the plurality of preliminary conductors together to form the rod-like conductor; and forming the insulation sheath to cover the rod-like conductor.

Abstract: There is provided a method for manufacturing an electrical wire. The electrical wire includes a rod-like conductor having a shape corresponding to a predetermined wiring route and also having rigidity to enable the rod-like conductor to hold the shape by itself, and an insulation sheath covering the rod-like conductor. The method includes: preparing a plurality of rod-like preliminary conductors having the rigidity so as to correspond to a plurality of sub routes into which the wiring route is divided; processing at least one of the plurality of preliminary conductors into a shape conforming to the corresponding sub routes; connecting the plurality of preliminary conductors to form the rod-like conductor; and forming the insulation sheath to cover the rod-like conductor.

Abstract: There is provided a wire harness and a manufacturing method thereof. A wire harness routed in a vehicle body is provided with an electric wire and a metallic shield pipe in which the electric wire is inserted. The shield pipe has a rigidity that enables self-maintenance of an after-bent shape. The shield pipe is bent with the electric wire being inserted therein so as to form the shield pipe in a shape conforming to piping to be assembled to the vehicle body.

Abstract: There is provided a wire harness and a manufacturing method thereof. A wire harness routed in a vehicle body is provided with an electric wire and a metallic shield pipe in which the electric wire is inserted. The shield pipe has a rigidity that enables self-maintenance of an after-bent shape. The shield pipe is bent with the electric wire being inserted therein so as to form the shield pipe in a shape conforming to piping to be assembled to the vehicle body.

Abstract: A wire harness includes a plurality of electric wires, a plurality of tubular metal pipes corresponding the number to the plurality of electric wires, each of the plurality of electric wires being inserted through respective one of the plurality of tubular metal pipes, a connector configured to be connected to end portions of the plurality of electric wires, and a tubular metal connecting portion provided at a pipe end portion of each of the plurality of pipes and connected to the connector. Each of the pipes has a rigidity capable of self-holding a bent shape thereof when each of the pipes are bent. The connecting portion has a flexibility incapable of self-holding a bent shape thereof when the connecting portion is bent.

Abstract: A wire harness includes a plurality of electric wires, a plurality of tubular metal pipes corresponding the number to the plurality of electric wires, each of the plurality of electric wires being inserted through respective one of the plurality of tubular metal pipes, a connector configured to be connected to end portions of the plurality of electric wires, and a tubular metal connecting portion provided at a pipe end portion of each of the plurality of pipes and connected to the connector. Each of the pipes has a rigidity capable of self-holding a bent shape thereof when each of the pipes are bent. The connecting portion has a flexibility incapable of self-holding a bent shape thereof when the connecting portion is bent.

Abstract: A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 1 (LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit 2 of the 4-bit counter, four PMOS transistors to Bit 3, and eight PMOS transistors to Bit 4 (MSB). Then, the weighting selection circuit selects transistors P3-1 to P3-30 based on the counted value CNTp output from the 4-bit counter.

Abstract: A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 1 (LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit 2 of the 4-bit counter, four PMOS transistors to Bit 3, and eight PMOS transistors to Bit 4 (MSB). Then, the weighting selection circuit selects transistors P3-1 to P3-30 based on the counted value CNTp output from the 4-bit counter.

Abstract: An NMOS impedance adjustment circuit has a comparator circuit for comparing with a reference electric potential VREFn a divided voltage potential Vin produced by an NMOS array and an external reference resistance. The NMOS array simulates the impedance of an output buffer circuit on the basis of the comparison result. The comparator circuit has three differential circuits. Three 2-input NAND gates and a single three-input NAND gate take the majority of output values of the differential circuits and output the result from the comparator circuit. A reduction of impedance adjustment precision caused by variability within the chip can thereby be inhibited.

Abstract: An NMOS impedance adjustment circuit has a comparator circuit for comparing with a reference electric potential VREFn a divided voltage potential Vin produced by an NMOS array and an external reference resistance. The NMOS array simulates the impedance of an output buffer circuit on the basis of the comparison result. The comparator circuit has three differential circuits. Three 2-input NAND gates and a single three-input NAND gate take the majority of output values of the differential circuits and output the result from the comparator circuit. A reduction of impedance adjustment precision caused by variability within the chip can thereby be inhibited.

Abstract: An impedance adjustment circuit has an external resistor, a comparator which compares the potential of one terminal of the external resistor with a predetermined voltage, a counter whose counted value changes in accordance with an output from the comparator and which outputs a control signal corresponding to the counted value, an NMOS array whose value of resistance changes in accordance with the control signal and which is connected to one terminal of the external resistor and an NMOS arbitration circuit which detects an output from the NMOS comparator a plurality of times and outputs a signal determined by a majority decision logic taken on the detected signals to the counter.

Abstract: An impedance adjustment circuit has an external resistor, a comparator which compares the potential of one terminal of the external resistor with a predetermined voltage, a counter whose counted value changes in accordance with an output from the comparator and which outputs a control signal corresponding to the counted value, an NMOS array whose value of resistance changes in accordance with the control signal and which is connected to one terminal of the external resistor and an NMOS arbitration circuit which detects an output from the NMOS comparator a plurality of times and outputs a signal determined by a majority decision logic taken on the detected signals to the counter.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: An output circuit has an n-channel constant voltage circuit and p-channel constant voltage circuit. The output circuit includes a p-channel MOS transistor and an n-channel MOS transistor at the output stage thereof. The n-channel constant voltage circuit controls the drive of the p-channel MOS transistor, and causes current flowing through the p-channel MOS transistor so that current path through the p-channel MOS transistor to be constant or substantially constant. The p-channel constant voltage circuit controls the drive of the n-channel MOS transistor, and causes current flowing through the n-channel MOS transistor so that current path through the n-channel MOS transistor to be constant or substantially constant.

Abstract: The invention provides a semiconductor circuit which can accept signals of various levels and operate at a high speed with low power dissipation. The semiconductor circuit includes a PMOS differential circuit having two inputs one of which is connected to a first input terminal and the other of which is connected to a second input terminal, an NMOS differential circuit having two inputs one of which is connected to the first input terminal and the other of which is connected to the second input terminal, and an output circuit operable in response to differential outputs of the PMOS differential circuit and the NMOS differential circuit for preventing, when a current path is formed between an output terminal and a power supply terminal, formation of a current path between a ground terminal and the output terminal, but preventing, when a current path is formed between the output terminal and the ground terminal, formation of a current path between the power supply terminal and the output terminal.

Abstract: An output amplitude regulating circuit comprises a first MOS differential circuit, with a first MOS transistor connected between an output terminal of the first MOS differential circuit and a power supply. The circuit also includes a second MOS differential circuit having a first input terminal that receives a reference electric potential, and a second MOS transistor that is connected between the power supply and a second input terminal of the second MOS differential circuit, and is connected to a reference electric potential via a third MOS transistor and a current source. In the circuit, output terminals of the first and second MOS transistors are used to regulate an output amplitude from the output terminal of the first MOS differential circuit.

Abstract: A highly reliable connection structure of a bundle of more than two coil leading-out wires and a wire bundling terminal is provided by contacting and fixing at least a part of a circumferential surface of each of the coil leading-out wires to an inside wall of the wire bundling terminal. Further, a small size motor and an alternator for a vehicle utilize the connection structure.

Abstract: A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal.