Patents by Inventor Takashi Oguri

Takashi Oguri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5382842
    Abstract: A BiMIS logic circuit includes a first bipolar junction transistor (BJT), a second BJT, a P-channel MIS transistor (PMIS), and an N-channel NMIS transistor (NMIS). A node between the first and second BJTs is connected to a first output terminal, and a node between the PMIS and the NMIS is connected to a second output terminal. When the potentials which cause the PMIS to turn ON and the NMIS to turn OFF are applied, a potential at the second output terminal rises to the power supply potential. The potential at the first output terminal assumes a potential lower than the power supply potential by a turn-on voltage (V.sub.F) of the BJT. When the potentials which cause the NMIS to turn ON and the PMIS to turn OFF are applied, the second output terminal and a node between the NMIS and the second BJT are caused to become conductive whereby the potential at the second output terminal falls and the potential at the node rises and both the potentials are equalized.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: January 17, 1995
    Assignee: NEC Corporation
    Inventor: Takashi Oguri
  • Patent number: 5357154
    Abstract: A level converter circuit, in which a bipolar transistor for raising an output voltage is switched on or off by a logical-BiMIS construction, and a MIS transistor for falling the output voltage is also switched on or off by a logic circuit and a charge discharge means 50 so as to reduce a propagation delay time, to raise a driving ability, to prevent a steady state current and to reduce a dissipation current.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: October 18, 1994
    Assignee: NEC Corporation
    Inventor: Takashi Oguri
  • Patent number: 5345132
    Abstract: An object of the invention is to, in a vehicular alternating current (AC) dynamo, reduce an influence of vibration on a brush during operation, thereby preventing the brush from wobbling, cracking or causing other damages, also to make the brush sufficiently exposed to cooling air during operation, thereby preventing the brush temperature from rising excessively. In the vehicular AC dynamo, by virtue of a pressing force produced upon a tubular cover integral with a fan guide being fixed to a rear bracket through a seal member, an abutting end surface of a projection of the tubular cover is axially abutted with an inner abutting surface of a recess of the brush holder for pressing and fixing said brush holder against and to the rear bracket.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: September 6, 1994
    Assignees: Hitachi Automotive Engineering, Hitachi, Ltd. and Co., Ltd.
    Inventors: Susumu Sasaki, Hisashi Wada, Takashi Oguri, Susumu Terumoto, Akihiro Saito
  • Patent number: 5300833
    Abstract: In the conventional configuration, when using circuits with different logical amplitude levels in mixture, the level converter circuit has been necessarily required, and this has been an element preventing the speeding up. Also when holding the ECL interface and the TTL interfaces in common, the level converter circuit is useless and the total size gets larger. In the present invention, for the semiconductor circuit mixed with the input buffer 1 receiving the signal amplitude voltage of the ECL interface, the input buffer 3 receiving the signal amplitude voltage of the TTL interface, and the MIS or BiMIS driver 2, the level converter circuit is not required by holding each signal amplitude voltage in Common, and it can be speeded up as much as the delayed time caused by the level converter circuit.
    Type: Grant
    Filed: January 15, 1993
    Date of Patent: April 5, 1994
    Assignee: Nec Corporation
    Inventor: Takashi Oguri
  • Patent number: 5254887
    Abstract: A level converter is of a three-stage circuit arrangement composed of an ECL circuit, a pair of emitter followers and a pair of level converting circuits. Each level converting circuit converts the logic level of an output signal from the ECL circuit into the logic level of a MIS or BiMIS output signal. Each level converting circuit has an input stage comprising an inverter composed of a P-type MIS transistor and an N-type MIS transistor, whose gates are supplied with the input signal, to be converted in level, from the ECL circuit. The small amplitude of the supplied input signal is fully swung to completely turn on or turn off a bipolar transistor in the output stage of the level converting circuit, thereby producing an output signal of MIS or BiMIS logic level.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: October 19, 1993
    Assignee: NEC Corporation
    Inventor: Takashi Oguri
  • Patent number: 4942835
    Abstract: An overlock sewing machine with a looper-thread guide mechanism of this invention is characterized by thread guide passages that are provided in the front face of the sewing machine body, and that go from thread tension disks toward loopers. By feeding looper thread along the thread guide passages, the looper thread is easily guided from a thread supply source, through the tension disks and a takeup, toward the loopers. Thus, the loopers can be threaded easily, quickly, and precisely.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: July 24, 1990
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takashi Oguri