Abstract: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.

Abstract: Access to various types of resources is controlled efficiently, thereby enhancing the throughput. A storage system includes: a disk device for providing a volume for storing data to a host system; a channel adapter for writing data from the host system to the disk device via a cache memory; a disk adapter for transferring data to and from the disk device; and at least one processor package including a plurality of processors for controlling the channel adapter and the disk adapter; wherein any one of the processor packages includes a processor for incorporatively transferring related types of ownership based on specific control information for managing the plurality of types of ownership for each of the plurality of types of resources.

Abstract: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.

Abstract: A storage controller having a plurality of storage device and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, release the certain storage area from mapping to a logical area in the plurality of virtual volume, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volume as a destination of another write access from the information processing apparatus.

Abstract: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.

Abstract: Access to various types of resources is controlled efficiently, thereby enhancing the throughput. A storage system includes: a disk device for providing a volume for storing data to a host system; a channel adapter for writing data from the host system to the disk device via a cache memory; a disk adapter for transferring data to and from the disk device; and at least one processor package including a plurality of processors for controlling the channel adapter and the disk adapter; wherein any one of the processor packages includes a processor for incorporatively transferring related types of ownership based on specific control information for managing the plurality of types of ownership for each of the plurality of types of resources.

Abstract: Provided is a storage subsystem capable of speeding up the input/output processing for a cache memory. Microprocessor Packages manage information related to a VDEV ownership for controlling virtual devices and a cache segment ownership for controlling cache segments in units of Microprocessor Packages, and one Microprocessor among multiple Microprocessors belonging to the determined Microprocessor Package to perform input/output processing for the virtual devices searches cache control information stored in the Package Memory without searching the cache control information in the shared memory, and if data exists in the cache memory, accesses the cache memory, and if it does not, accesses the virtual devices.

Abstract: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.

Abstract: A storage controller of the present invention partitions and allocates a virtual memory area to each of a plurality of functions operating simultaneously. Microprocessors inside a higher-level communications controller can respectively execute a plurality of program products. A virtual memory created using a local memory is partitioned into a plurality of areas. The partitioned areas are allocated to the respective program products via queues.

Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.

Abstract: The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions. A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be used by partitioning the cache region of a cache memory. Management information required to manage the data stored in the cache memory is allocated to each CLPR in accordance with the attribute of the segment or slot. The clean queue and clean counter, which manage the segments in a clean state, are provided in each CLPR. The dirty queue and dirty counter are used jointly by all the CLPR. The free queue, classification queue, and BIND queue are applied jointly to all the CLPR, only the counters being provided in each CLPR.

Abstract: A storage control technique with which, even if not data, but only its management information is deleted, a host system can recognize storage areas storing unnecessary data and so use them effectively. When a file system in the host system deletes the management information for data stored in a page in a pool volume, a control circuit writes ‘0’ in all the areas in the deletion target page in response to a command from the host system. The control circuit then detects the page where ‘0’ is written in all of its areas and releases it from allocation to the corresponding virtual volume.

Abstract: A storage control technique with which, even if not data, but only its management information is deleted, a host system can recognize storage areas storing unnecessary data and so use them effectively. When a file system in the host system deletes the management information for data stored in a page in a pool volume, a control circuit writes ‘0’ in all the areas in the deletion target page in response to a command from the host system. The control circuit then detects the page where ‘0’ is written in all of its areas and releases it from allocation to the corresponding virtual volume.

Abstract: The invention relates to a method of manufacturing a blow moulded component, particularly a component for motor vehicle equipment, wherein a component wall and an interior cavity are formed in a mould by blow molding of a plastic blank, wherein a reinforcing element extending in the interior cavity is fixed in rigidifying manner, in that during the blow molding a fastening section of the reinforcing element is joined to the component wall interiorly of said wall at a junction, and a further fastening section of the reinforcing element is joined to the structural wall in the region of an opening of the component wall at a second junction. The invention also relates to a blow moulded component, particularly a component for motor vehicle equipment and a blow mould for manufacturing a blow moulded component from a plastic blank.

Abstract: The present invention carries out cache management in such a manner that the management region required for cache management does not increase, and neither does the performance decline. It is possible to combine use of both a hierarchical directory method and a hash directory method, in order to manage cache data. In a hierarchical directory method, the desired data is retrieved by referring to respective tables T1 to T7, in succession. In a hash directory method, the desired data is reached by referring to a hash table TI0 and tables T4 to T7. Access conflicts between the respective methods are avoided by using the EDEV number and a portion of the VDEV number for a hash key. By combining use of both of these methods, it is possible to respond to cases where the storage capacity of the storage system has been increased, without having to raise the management region, and without causing a decline in performance.

Abstract: A digital Y signal compatible with a plurality of pixels in one frame unit is divided into a plurality of signal level regions for each constant signal level range by means of a histogram generator circuit, a rate of pixels included in each signal level to all the pixels is detected, and a histogram is generated. In addition, a correction coefficient is set, and the correction coefficient is stored in a correction coefficient storage circuit. In a computing circuit, a correction value relevant to a signal level in each signal level region is calculated in accordance with the histogram and correction coefficient, and input and output characteristics of the digital Y signal are adjusted on the basis of the calculated correction value. The digital Y signal is gamma-corrected by a Y-?correcting circuit in accordance with the input and output characteristics adjusted by the computing circuit.

Abstract: A storage controller of the present invention partitions and allocates a virtual memory area to each of a plurality of functions operating simultaneously. Microprocessors inside a higher-level communications controller can respectively execute a plurality of program products. A virtual memory created using a local memory is partitioned into a plurality of areas. The partitioned areas are allocated to the respective program products via queues.

Abstract: A storage control technique with which, even if not data, but only its management information is deleted, a host system can recognize storage areas storing unnecessary data and so use them effectively. When a file system in the host system deletes the management information for data stored in a page in a pool volume, a control circuit writes ‘0’ in all the areas in the deletion target page in response to a command from the host system. The control circuit then detects the page where ‘0’ is written in all of its areas and releases it from allocation to the corresponding virtual volume.

Abstract: The invention relates to a device for actuating the horn on steering wheels, comprising a steering wheel frame and at least one fixed horn contact provided thereon, and comprising a moving paddling support i.e. generator support and at least one horn contact, which is provided thereon and to which the fixed horn contact is assigned. The invention provides that the padding support i.e. the generator support is mounted on the steering wheel frame in a manner that enables it to pivot at a position.

Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.