Patents by Inventor Takashi Shiigi
Takashi Shiigi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11749675Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).Type: GrantFiled: January 7, 2021Date of Patent: September 5, 2023Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
-
Publication number: 20230067428Abstract: Provided is a test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal.Type: ApplicationFiled: July 13, 2022Publication date: March 2, 2023Inventors: Kenichi ISHII, Atsushi YOSHIDA, Tomonori MORI, Takashi SHIIGI
-
Patent number: 11456359Abstract: A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.Type: GrantFiled: August 29, 2016Date of Patent: September 27, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Yuichi Harada, Takashi Shiigi
-
Publication number: 20210134789Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).Type: ApplicationFiled: January 7, 2021Publication date: May 6, 2021Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
-
Patent number: 10916541Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).Type: GrantFiled: September 2, 2016Date of Patent: February 9, 2021Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
-
Patent number: 10784256Abstract: A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.Type: GrantFiled: September 30, 2016Date of Patent: September 22, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takashi Shiigi, Shoji Yamada, Yuichi Harada, Yasuyuki Hoshi
-
Patent number: 10504785Abstract: A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n+-type source region and a p+-type contact region of the main semiconductor element are connected by wiring by an anode electrode on a front surface of the silicon carbide base. The temperature sensing part, when the main semiconductor element is ON, is forward biased by drift current flowing in the main semiconductor element. The temperature sensing part, for example, is a poly-silicon diode constituted by a p-type poly-silicon layer and an n-type poly-silicon layer arranged on the front surface of the silicon carbide base. With such configuration, a semiconductor device having high reliability may be provided.Type: GrantFiled: May 25, 2018Date of Patent: December 10, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shoji Yamada, Takashi Shiigi, Yasuyuki Hoshi
-
Patent number: 10497784Abstract: A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part. The isolating part has a function of suppressing interference of the main semiconductor element and the current sensing part at the silicon carbide base. The isolating part is constituted by a trench provided a predetermined depth from a front surface of the silicon carbide base. An insulating film is provided in the trench, along inner walls of the trench. A poly-silicon layer is provided on the insulating film. With such a configuration, decreases in breakdown voltage of the current sensing part may be prevented.Type: GrantFiled: May 24, 2018Date of Patent: December 3, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Takashi Shiigi, Shoji Yamada
-
Patent number: 10490625Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.Type: GrantFiled: March 30, 2018Date of Patent: November 26, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shin'ichi Nakamata, Takashi Shiigi, Yasuyuki Hoshi, Yuichi Harada
-
Patent number: 10276666Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.Type: GrantFiled: August 30, 2017Date of Patent: April 30, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Masahito Otsuki, Shoji Yamada, Takashi Shiigi
-
Publication number: 20180350900Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.Type: ApplicationFiled: March 30, 2018Publication date: December 6, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shin'ichi NAKAMATA, Takashi SHIIGI, Yasuyuki HOSHI, Yuichi HARADA
-
Patent number: 10147792Abstract: A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.Type: GrantFiled: August 31, 2017Date of Patent: December 4, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Yuichi Harada, Takashi Shiigi
-
Patent number: 10103229Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 ?m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.Type: GrantFiled: October 12, 2016Date of Patent: October 16, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Yuichi Harada, Takashi Shiigi
-
Publication number: 20180277437Abstract: A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n+-type source region and a p+-type contact region of the main semiconductor element are connected by wiring by an anode electrode on a front surface of the silicon carbide base. The temperature sensing part, when the main semiconductor element is ON, is forward biased by drift current flowing in the main semiconductor element. The temperature sensing part, for example, is a poly-silicon diode constituted by a p-type poly-silicon layer and an n-type poly-silicon layer arranged on the front surface of the silicon carbide base. With such configuration, a semiconductor device having high reliability may be provided.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shoji YAMADA, Takashi SHIIGI, Yasuyuki HOSHI
-
Publication number: 20180277638Abstract: A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part. The isolating part has a function of suppressing interference of the main semiconductor element and the current sensing part at the silicon carbide base. The isolating part is constituted by a trench provided a predetermined depth from a front surface of the silicon carbide base. An insulating film is provided in the trench, along inner walls of the trench. A poly-silicon layer is provided on the insulating film. With such a configuration, decreases in breakdown voltage of the current sensing part may be prevented.Type: ApplicationFiled: May 24, 2018Publication date: September 27, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki HOSHI, Takashi SHIIGI, Shoji YAMADA
-
Patent number: 9997603Abstract: In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.Type: GrantFiled: August 25, 2017Date of Patent: June 12, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Hoshi, Yuichi Harada, Takashi Shiigi
-
Publication number: 20180006122Abstract: A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.Type: ApplicationFiled: August 31, 2017Publication date: January 4, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki HOSHI, Yuichi HARADA, Takashi SHIIGI
-
Publication number: 20170365665Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki HOSHI, Masahito OTSUKI, Shoji YAMADA, Takashi SHIIGI
-
Publication number: 20170352733Abstract: In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki HOSHI, Yuichi HARADA, Takashi SHIIGI
-
Publication number: 20170110544Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 ?m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.Type: ApplicationFiled: October 12, 2016Publication date: April 20, 2017Applicant: Fuji Electric Co., Ltd.Inventors: Yasuyuki HOSHI, Yuichi HARADA, Takashi SHIIGI