Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 ?m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.

Abstract: A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

Abstract: A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Abstract: The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n? region, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.

Abstract: In a semiconductor device, an edge termination region which surrounds an active region includes an electric field reduction mechanism including guard rings, first field plates which come into contact with the guard rings, and second field plates which are provided on the first field plates, with an interlayer insulating film interposed therebetween. The second field plate is thicker than the first field plate. A gap between the second field plates is greater than a gap between the first field plates. A barrier metal film is provided between the second field plate and the interlayer insulating film so as come into conductive contact with the second field plate. A gap between the barrier metal films is equal to the gap between the first field plates.

Abstract: A semiconductor device is disclosed. The semiconductor device is capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region that is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region that is disposed in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region that surrounds the p type diffusion region.

Abstract: The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n? region, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.

Abstract: A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Abstract: A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Abstract: In a semiconductor device, an edge termination region which surrounds an active region includes an electric field reduction mechanism including guard rings, first field plates which come into contact with the guard rings, and second field plates which are provided on the first field plates, with an interlayer insulating film interposed therebetween. The second field plate is thicker than the first field plate. A gap between the second field plates is greater than a gap between the first field plates. A barrier metal film is provided between the second field plate and the interlayer insulating film so as come into conductive contact with the second field plate. A gap between the barrier metal films is equal to the gap between the first field plates.

Abstract: A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less.

Abstract: A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less.

Abstract: A semiconductor device is disclosed. The semiconductor device is capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region that is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region that is disposed in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region that surrounds the p type diffusion region.

Abstract: A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.