Abstract: A display system includes a first memory and a display driver. The display system is configured to control the first memory to receive compensation information from the first memory with a first frequency and generate data signals for image data to be displayed on a display panel. The generation of the data signals comprises performing a compensation for the data signals based on the compensation information received from the first memory. The display driver is further configured to update pixels of the display panel with the data signals during an active display state. The display driver is further configured to generate updated compensation information based at least in part on the image data and the compensation information received from the first memory and transmit the updated compensation information to the first memory during the active display state with a second frequency lower than the first frequency.

Abstract: A power controlling circuit is assigned to each of a plurality of power domains of which power may be on/off-controlled, and which have a first hierarchical structure included in a semiconductor device, and these power controlling circuits are connected in accordance with a second hierarchical structure corresponding to the first hierarchical structure, and thereby, a power management unit controlling power supply to the plurality of power domains is configured, as a result that the power management unit performing power supply control depending on power control specification may be designed easily.

Abstract: A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data.

Abstract: There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.

Abstract: A semiconductor device includes first and second memory circuits that are disposed in different power source blocks and operate in synchronization with a clock, first and second delay circuits that are connected between output terminals of one memory circuits and input terminals of the other memory circuits, and a determination circuit that determines whether it is a situation that can cause malfunction based on an input signal and an output signal in the memory circuits and outputs a determination result as an error detection signal. To the first and second memory circuits, different initial values are given, and it is monitored whether a signal is sent and received between the memory circuits in a toggle state or not. Thus, occurrence of a situation that can cause malfunction can be simply and quickly detected.

Abstract: A power gating circuit is provided one by one corresponding to each of a plurality of power domains of which power may be on/off-controlled included in a semiconductor device, and these power gating circuits are connected in accordance with inclusion relation of the power domains, and thereby, a power management unit controlling power supply to the plurality of power domains is configured, as a result that the power management unit performing power supply control depending on power control specification may be designed easily.

Abstract: There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.

Abstract: A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data.

Abstract: A power gating circuit is provided one by one corresponding to each of a plurality of power domains of which power can be on/off-controlled included in a semiconductor device, and these power gating circuits are connected in accordance with inclusion relation of the power domains, and thereby, a power management unit controlling power supply to the plurality of power domains is configured, as a result that the power management unit performing power supply control depending on power control specification can be designed easily.

Abstract: A semiconductor device includes first and second memory circuits that are disposed in different power source blocks and operate in synchronization with a clock, first and second delay circuits that are connected between output terminals of one memory circuits and input terminals of the other memory circuits, and a determination circuit that determines whether it is a situation that can cause malfunction based on an input signal and an output signal in the memory circuits and outputs a determination result as an error detection signal. To the first and second memory circuits, different initial values are given, and it is monitored whether a signal is sent and received between the memory circuits in a toggle state or not. Thus, occurrence of a situation that can cause malfunction can be simply and quickly detected.

Abstract: A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus.

Abstract: A semiconductor integrated circuit includes a module configured to operate based on a clock signal, a voltage controlling unit configured to change a power supply voltage supplied to the module, a clock generating unit configured to supply the clock signal to the module, and a test circuit configured to operate at the power supply voltage based on the clock signal to emulate a delay of a critical path provided in the module, thereby testing whether the module properly operates at the power supply voltage, wherein the clock generating unit supplies a different signal, in place of the clock signal, to the module while the voltage controlling unit is changing the power supply voltage.

Abstract: A semiconductor integrated circuit device comprises an internal bus, a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function, and a clock generating unit generating a reference clock and a clock sync signal which indicates positions of valid clock edges in the reference clock, the clock generating unit supplying the reference clock and the clock sync signal to the internal modules. At least one of the internal modules is provided with a sync control module which generates an internal clock based on the reference clock and the clock sync signal.

Abstract: A semiconductor integrated circuit includes a CPU core unit, an on-chip-bus unit coupled to the CPU core unit, a on-chip memory directly connected to the on-chip-bus unit, and a voltage controlling unit configured to control a power supply voltage for driving the CPU core circuit and to output a boot switch signal, the on-chip-bus unit configured to switch a boot address between the memory and another device in response to a state of the boot switch signal when the CPU core unit fetches boot program instructions from the boot address.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: A semiconductor integrated circuit includes a module configured to operate based on a clock signal, a voltage controlling unit configured to change a power supply voltage supplied to the module, a clock generating unit configured to supply the clock signal to the module, and a test circuit configured to operate at the power supply voltage based on the clock signal to emulate a delay of a critical path provided in the module, thereby testing whether the module properly operates at the power supply voltage, wherein the clock generating unit supplies a different signal, in place of the clock signal, to the module while the voltage controlling unit is changing the power supply voltage.

Abstract: A semiconductor integrated circuit includes a CPU core unit, an on-chip-bus unit coupled to the CPU core unit, a on-chip memory directly connected to the on-chip-bus unit, and a voltage controlling unit configured to control a power supply voltage for driving the CPU core circuit and to output a boot switch signal, the on-chip-bus unit configured to switch a boot address between the memory and another device in response to a state of the boot switch signal when the CPU core unit fetches boot program instructions from the boot address.

Abstract: A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus.

Abstract: A semiconductor integrated circuit device comprises an internal bus, a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function, and a clock generating unit generating a reference clock and a clock sync signal which indicates positions of valid clock edges in the reference clock, the clock generating unit supplying the reference clock and the clock sync signal to the internal modules. At least one of the internal modules is provided with a sync control module which generates an internal clock based on the reference clock and the clock sync signal.

Abstract: In a semiconductor integrated circuit device, a first circuit has a clock generating circuit which generates a clock signal. A second circuit receives the clock signal from the clock generating circuit. The first circuit maintains the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another frequency. The first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.