Abstract: In a semiconductor integrated circuit device, a first circuit has a clock generating circuit which generates a clock signal. A second circuit receives the clock signal from the clock generating circuit. The first circuit maintains the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another frequency. The first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: In a semiconductor integrated circuit device, a first circuit has a clock generating circuit which generates a clock signal. A second circuit receives the clock signal from the clock generating circuit. The first circuit maintains the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another frequency. The first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.

Abstract: A DSP 20 receives a serial audio signal DATi synchronized with a external clock .phi.i with the same cycle as that of the internal clock .phi.o and a LR identification signal LRi synchronized in units of words of the serial audio signal DATi, processes the serial audio signal LRi with synchronizing to the internal clock .phi.o and provides a serial audio signal DATo and a LR identification signal LRo. A DSP 20 includes a D flip-flop 11 for detecting and holding the rising edge of the LR identification signal LRi, and a counter 15 for counting the internal clock .phi.o after this detecting to provide the periodic LR identification signal LRo from its inverse output *Q.