Patents by Inventor Takashi Shinohe
Takashi Shinohe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967618Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.Type: GrantFiled: June 6, 2022Date of Patent: April 23, 2024Assignee: FLOSFIA INC.Inventors: Isao Takahashi, Takashi Shinohe, Rie Tokuda, Masaya Oda, Toshimi Hitora
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Publication number: 20240021669Abstract: Provided is a semiconductor device including: at least a semiconductor layer having a corundum structure, the semiconductor layer including a first surface having at least a first side and a second side shorter than the first side, the first surface being a c-plane or an m-plane, a direction of the first side being a direction of a c-axis or a direction of an m-axis.Type: ApplicationFiled: July 12, 2022Publication date: January 18, 2024Inventors: Isao TAKAHASHI, Kazuyoshi NORIMATSU, Takashi SHINOHE
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Patent number: 11855135Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.Type: GrantFiled: October 22, 2021Date of Patent: December 26, 2023Assignee: FLOSFIA INC.Inventors: Mitsuru Okigawa, Hideaki Yanagida, Takashi Shinohe
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Publication number: 20230335581Abstract: Provided a semiconductor device having a structure to suppress hole injections into the gate insulator. A semiconductor device including a gate insulating film, a hole blocking layer placed in contact with the gate insulating film, and an oxide semiconductor layer placed in contact with the hole blocking layer, wherein the hole blocking layer is located between the gate insulating film and the oxide semiconductor layer.Type: ApplicationFiled: June 9, 2023Publication date: October 19, 2023Inventors: Yasushi HIGUCHI, Takashi SHINOHE
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Publication number: 20230290832Abstract: Provided is a semiconductor device, including: a gate electrode having at least a part buried in a semiconductor layer; a deep p layer having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and a channel layer, wherein: the deep p layer is formed by a crystalline oxide semiconductor; and a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer.Type: ApplicationFiled: April 11, 2023Publication date: September 14, 2023Inventors: Yasushi HIGUCHI, Masahiro SUGIMOTO, Takashi SHINOHE, Isao TAKAHASHI, Hideo MATSUKI, Fusao HIROSE
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Publication number: 20230253462Abstract: Provided is a crystalline oxide film including: a plane tilted from a c-plane as a principal plane; gallium; and a metal in Group 9 of the periodic table, the metal in Group 9 of the periodic table among all metallic elements in the film having an atomic ratio of equal to or less than 23%.Type: ApplicationFiled: February 9, 2023Publication date: August 10, 2023Inventors: Takashi SHINOHE, Hiroyuki ANDO, Yasushi HIGUCHI, Shinpei MATSUDA, Kazuya TANIGUCHI, Hiroki WATANABE, Hideo MATSUKI
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Publication number: 20230207431Abstract: Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel; and a die pad on which at least one of the PN junction diodes and the Schottky barrier diode are mounted commonly.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Hideaki YANAGIDA, Takashi SHINOHE, Hiroyuki ANDO, Yusuke MATSUBARA, Hidehito KITAKADO
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Publication number: 20230207541Abstract: Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a plurality of resistance elements connected respectively to the PN junction diodes in parallel and connected to each other in series; and a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Hideaki YANAGIDA, Takashi SHINOHE, Hiroyuki ANDO, Yusuke MATSUBARA, Hidehito KITAKADO
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Patent number: 11670688Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).Type: GrantFiled: November 15, 2018Date of Patent: June 6, 2023Assignee: FLOSFIA INC.Inventors: Tokiyoshi Matsuda, Masahiro Sugimoto, Takashi Shinohe
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Patent number: 11594601Abstract: A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.Type: GrantFiled: November 15, 2018Date of Patent: February 28, 2023Assignee: FLOSFIA INC.Inventors: Tokiyoshi Matsuda, Masahiro Sugimoto, Takashi Shinohe
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Publication number: 20220416651Abstract: Provided is a power conversion device converting power and supplying the converted power to a load, the power conversion device including: a power conversion circuit connected to the load and configured to supply/receive the power; a coil configured to detect a current passing through the power conversion circuit and to output a voltage corresponding to the detected current; an integration circuit configured to integrate the voltage output from the coil to generate a voltage signal corresponding to a variation of the current; and a control device configured to generate a control signal to the power conversion circuit based on the voltage signal output from the integration circuit.Type: ApplicationFiled: August 25, 2022Publication date: December 29, 2022Inventors: Masato ITO, Masaya MITAKE, Yukio YAMASHITA, Shogo MIZUMOTO, Hideaki YANAGIDA, Takashi SHINOHE
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Publication number: 20220384663Abstract: Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, having a corundum structure, the conductive substrate having a larger area than the oxide semiconductor film.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Applicant: FLOSFIA INC.Inventors: Yusuke MATSUBARA, Osamu IMAFUJI, Hiroyuki ANDO, Hideki TAKEHARA, Takashi SHINOHE, Mitsuru OKIGAWA
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Publication number: 20220376056Abstract: Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, containing gallium, the conductive substrate having a larger area than the oxide semiconductor film.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Yusuke MATSUBARA, Osamu IMAFUJI, Hiroyuki ANDO, Hideki TAKEHARA, Takashi SHINOHE, Mitsuru OKIGAWA
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Patent number: 11495695Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.Type: GrantFiled: July 10, 2019Date of Patent: November 8, 2022Assignee: FLOSFIA INC.Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Koji Amazutsumi
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Patent number: 11488821Abstract: The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.Type: GrantFiled: June 21, 2019Date of Patent: November 1, 2022Assignee: FLOSFIA INC.Inventors: Isao Takahashi, Takashi Shinohe
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Publication number: 20220344477Abstract: Provided is a semiconductor device including; at least a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of a c-axis in the semiconductor layer being the first direction.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Isao TAKAHASHI, Kazuyoshi NORIMATSU, Takashi SHINOHE
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Publication number: 20220302263Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Isao TAKAHASHI, Takashi SHINOHE, Rie TOKUDA, Masaya ODA, Toshimi HITORA
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Patent number: 11450745Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.Type: GrantFiled: February 5, 2020Date of Patent: September 20, 2022Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Johji Nishio, Takashi Shinohe
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Patent number: 11450774Abstract: A semiconductor device with an enhanced semiconductor characteristics that is useful for power devices. A semiconductor device including: a semiconductor region; a barrier electrode arranged on the semiconductor region; and two or more adjustment regions of barrier height that are on a surface of the semiconductor region and arranged between the semiconductor region and the barrier electrode, the adjustment regions are configured such that barrier height at an interface between the adjustment regions and the barrier electrode is higher than barrier height at an interface between the semiconductor region and the barrier electrode.Type: GrantFiled: July 6, 2018Date of Patent: September 20, 2022Assignee: FLOSFIA INC.Inventors: Masahiro Sugimoto, Isao Takahashi, Hitoshi Kambara, Takashi Shinohe, Toshimi Hitora
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Patent number: 11393906Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.Type: GrantFiled: November 7, 2017Date of Patent: July 19, 2022Assignee: FLOSFIA INC.Inventors: Isao Takahashi, Takashi Shinohe, Rie Tokuda, Masaya Oda, Toshimi Hitora