Patents by Inventor Takashi Shinohe

Takashi Shinohe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190103465
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 4, 2019
    Inventors: Tokiyoshi MATSUDA, Takashi SHINOHE, Shingo YAGYU, Takuto IGAWA
  • Publication number: 20190074178
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes a first semiconductor layer that is an electron-supply layer containing as a major component a first semiconductor crystal with a metastable crystal structure; and a second semiconductor layer that is an electron-transit layer containing as a major component a second semiconductor crystal with a hexagonal crystal structure. The first semiconductor crystal contained in the first semiconductor layer is different in composition from the second semiconductor crystal comprised in the second semiconductor layer.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Inventors: Riena JINNO, Shizuo FUJITA, Kentaro KANEKO, Tokiyoshi MATSUDA, Takashi SHINOHE, Toshimi HITORA
  • Publication number: 20190067492
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer including a first semiconductor as a major component, an i-type semiconductor layer including a second semiconductor as a major component and a p-type semiconductor layer including a third semiconductor as a major component. The second semiconductor contains a corundum-structured oxide semiconductor.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 28, 2019
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Toshimi HITORA
  • Publication number: 20190067426
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer, an i-type semiconductor layer and a p-type semiconductor layer. The i-type semiconductor layer includes an oxide semiconductor as a major component. The oxide semiconductor that is included as the major component of the i-type semiconductor layer includes at least one metal selected from among aluminum, indium, and gallium.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 28, 2019
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Toshimi HITORA
  • Publication number: 20190057865
    Abstract: According to an aspect of a present inventive subject matter, a crystalline film includes a crystalline metal oxide as a major component, the crystalline film includes a corundum structure, a surface area that is 9 ?m2 or more, and a dislocation density that is less than 5×106cm?2.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190055646
    Abstract: According to an aspect of a present inventive subject matter, a method for producing a crystalline film includes gasifying a metal source to turn the metal source into a metal-containing raw-material gas; supplying the metal-containing raw-material gas and an oxygen-containing raw-material gas into a reaction chamber onto a substrate; and supplying a reactive gas into the reaction chamber onto the substrate to form a crystalline film under a gas flow of the reactive gas.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190055667
    Abstract: According to an aspect of a present inventive subject matter, a method for producing a crystalline film includes; gasifying a metal source containing a metal to turn the metal source into a metal-containing raw-material gas; supplying the metal-containing raw-material gas and an oxygen-containing raw-material gas into a reaction chamber onto a substrate including a buffer layer; and supplying a reactive gas into the reaction chamber onto the substrate to form a crystalline film on the substrate under a gas flow of the reactive gas.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190057866
    Abstract: According to an aspect of a present inventive subject matter, a crystal includes: a corundum-structured oxide semiconductor as a major component, the corundum-structured oxide semiconductor including gallium and/or indium and doped with a dopant including germanium; a principal plane; a carrier concentration that is 1×1018/cm3 or more; and an electron mobility that is 20 cm2/Vs or more.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Patent number: 10177251
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takashi Shinohe, Ryosuke Iijima
  • Patent number: 10177009
    Abstract: A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Tatsuo Shimizu, Takashi Shinohe
  • Publication number: 20190006472
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ?-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ?-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 3, 2019
    Inventors: Tokiyoshi MATSUDA, Takashi SHINOHE, Toshimi HITORA
  • Publication number: 20180337275
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: November 22, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Takashi SHINOHE, Ryosuke llJIMA
  • Patent number: 10079282
    Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 18, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Chiharu Ota, Kazuto Takao, Takashi Shinohe
  • Publication number: 20180190775
    Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
  • Patent number: 9978842
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 22, 2018
    Assignees: Kabushiki Kaisha Toshiba, National Institute of Advanced Industrial Science and Technology, FUJI ELECTRIC CO., LTD.
    Inventors: Keiko Ariyoshi, Tatsuo Shimizu, Takashi Shinohe, Junji Senzaki, Shinsuke Harada, Takahito Kojima
  • Patent number: 9941361
    Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
  • Patent number: 9837488
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer; a second semiconductor layer having a larger band gap than the first semiconductor layer; a third semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode being in contact with the third semiconductor layer; a second electrode being in contact with the third semiconductor layer; and a third electrode provided between the third semiconductor layer in contact with the first electrode, the second semiconductor layer directly below the first electrode, and the first semiconductor layer directly below the first electrode, and the third semiconductor layer in contact with the second electrode, the second semiconductor layer directly below the second electrode, and the first semiconductor layer directly below the second electrode, being in contact with the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer via insulating film.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: December 5, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Masahiko Kuraguchi, Takashi Shinohe
  • Publication number: 20170338125
    Abstract: A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 23, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji NISHIO, Tatsuo SHIMIZU, Takashi SHINOHE
  • Patent number: 9825121
    Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Keiko Ariyoshi, Tatsuo Shimizu, Kazuto Takao, Takashi Shinohe
  • Patent number: 9812589
    Abstract: A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first SiC region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 1×1018 cm?3 or less, and a conductive layer provided between the first SiC region and the first metal layer and containing titanium (Ti), oxygen (O), and at least one element selected from the group consisting of vanadium (V), niobium (Nb), and tantalum (Ta).
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takashi Shinohe