Abstract: According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.

Abstract: According to one embodiment, a transistor includes: a structural body; an insulating film; a control electrode; a first electrode; and a second electrode. The structural body includes a first through a third semiconductor regions, and includes a compound semiconductor having a first and a second elements. The first electrode is electrically continuous with the third semiconductor region. The second electrode is electrically continuous with the first semiconductor region. The structural body has a first region provided above a lower end of the second semiconductor region and a second region other than the first region. The first region is a region formed by making a ratio of concentration of source gas of the second element to concentration of source gas of the first element larger than 1.0. Impurity concentration of the first conductivity type in the first region is higher than that in the second region.

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

Abstract: An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a substrate; and growing a p-type SiC single-crystal layer on the surface of the substrate from a liquid phase that contains Si (silicon), C (carbon), a p-type impurity, and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a first combination that is at least one combination selected from Al (aluminum) and N (nitrogen), Ga (gallium) and N (nitrogen), and In (indium) and N (nitrogen), and/or a second combination of B (boron) and P (phosphorus), the ratio of the concentration of the element D to the concentration of the element A in the first or second combination being higher than 0.33 but lower than 1.0.

Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.

Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a first insulating section, and a second insulating section. The first semiconductor region includes silicon carbide, is of a first conductivity type and includes first and second parts. The second semiconductor region includes silicon carbide, is of a second conductivity type and is provided on the second part. The third semiconductor region includes silicon carbide, is of the first conductivity type and is provided on the second semiconductor region. The first electrode is provided on the first part and the third semiconductor region. The first insulating section is provided on the third semiconductor region and juxtaposed with the first electrode. The second insulating section is provided between the first electrode and the first part and between the first electrode and the first insulating section.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a first electrode. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region, and is of the second conductivity type. The third semiconductor region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type, and satisfies 1<D2/D1<3, where D1 is a first concentration of the first impurity, and D2 is a second concentration of the second impurity. The first electrode is provided on the first, second, and third semiconductor regions. The first electrode is in contact with the second and third semiconductor regions.

Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode.

Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.

Abstract: An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

Abstract: A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×1017 cm?3 and not higher than 1×1022 cm?3, a first electrode, and a second electrode.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.