Abstract: In a plasma processing apparatus, a table has a wafer support to hold a wafer and a peripheral segment surrounding the wafer support and having through-holes. The peripheral segment has an upper surface lower than that of the wafer support. An outer focus ring is disposed over the peripheral segment and has a recess or a cutout at an inner portion of the outer focus ring, and the recess or cutout has through-holes. An inner focus ring is disposed in the recess or cutout of the outer focus ring. Lift pins respectively extend through the through-holes of the peripheral segment and the through-holes of the recess or cutout of the outer focus ring. Shift mechanisms control shift of the respective lift pins.

Abstract: A dielectric member that is attached to a lower surface of a stage is provided. The stage includes a base provided with a base channel through which a heat exchange medium passes. The dielectric member includes at least one first component including a passage that is connected to the base channel, and a second component surrounding the first component.

Abstract: A semiconductor storage device includes a memory cell unit which includes memory cell arrays including a plurality of memory cells; a peripheral circuit which performs voltage transmission control including a write operation, a read operation, and an erasing operation with respect to the memory cell unit; and signal lines which connect the peripheral circuit to the memory cell unit, and at least a portion of the signal lines is formed in a non-facing region, the non-facing region being a region where the memory cell unit does not face the peripheral circuit, the non-facing region being in a peripheral region formed around a periphery of the memory cell arrays of the memory cell unit.

Abstract: A substrate processing apparatus includes a stage, a light source, an optical assembly, a light receiver, and controller circuitry. The stage includes a first placing surface on which a substrate is to be placed, and a second placing surface that surrounds the first placing surface and on which a focus ring is to be placed. The optical assembly focuses light from the light source on a lower surface position, which is a position of a lower surface of the focus ring placed on the second placing surface. The light receiver receives light from the lower surface position. The controller circuitry detects at least one of a presence and an absence of the focus ring on the second placing surface, based on light received by the light receiver.

Abstract: A semiconductor storage device includes a memory cell unit which includes memory cell arrays including a plurality of memory cells; a peripheral circuit which performs voltage transmission control including a write operation, a read operation, and an erasing operation with respect to the memory cell unit; and signal lines which connect the peripheral circuit to the memory cell unit, and at least a portion of the signal lines is formed in a non-facing region, the non-facing region being a region where the memory cell unit does not face the peripheral circuit, the non-facing region being in a peripheral region formed around a periphery of the memory cell arrays of the memory cell unit.

Abstract: A dielectric member that is attached to a lower surface of a stage is provided. The stage includes a base provided with a base channel through which a heat exchange medium passes. The dielectric member includes at least one first component including a passage that is connected to the base channel, and a second component surrounding the first component.

Abstract: An edge ring includes a first edge ring, and a second edge ring that has a side surface adjacent to a side surface of the first edge ring and is movable in a vertical direction along the side surface of the first edge ring. Further, the side surface of the first edge ring and the side surface of the second edge ring at least partially face each other in a movement range of the second edge ring.

Abstract: A substrate processing apparatus includes a stage, a light source, an optical assembly, a light receiver, and controller circuitry. The stage includes a first placing surface on which a substrate is to be placed, and a second placing surface that surrounds the first placing surface and on which a focus ring is to be placed. The optical assembly focuses light from the light source on a lower surface position, which is a position of a lower surface of the focus ring placed on the second placing surface. The light receiver receives light from the lower surface position. The controller circuitry detects at least one of a presence and an absence of the focus ring on the second placing surface, based on light received by the light receiver.

Abstract: In a plasma processing apparatus, a table has a wafer support to hold a wafer and a peripheral segment surrounding the wafer support and having through-holes. The peripheral segment has an upper surface lower than that of the wafer support. An outer focus ring is disposed over the peripheral segment and has a recess or a cutout at an inner portion of the outer focus ring, and the recess or cutout has through-holes. An inner focus ring is disposed in the recess or cutout of the outer focus ring. Lift pins respectively extend through the through-holes of the peripheral segment and the through-holes of the recess or cutout of the outer focus ring. Shift mechanisms control shift of the respective lift pins.

Abstract: A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of: arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip; arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis; shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts; forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semi

Abstract: A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.

Abstract: A semiconductor storage device comprises a memory cell array including memory cells, and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to the gate of the first switching element a voltage for turning the first switching element ON; a second switching element and a third switching element connected in series between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to the gates of the second and third switching elements a voltage for turning the second and third switching elements ON; and a first timing shift circuit connected between the gate of the third switching element and the second reference voltage sour

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: A semiconductor storage device comprises a memory cell array including memory cells, and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to the gate of the first switching element a voltage for turning the first switching element ON; a second switching element and a third switching element connected in series between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to the gates of the second and third switching elements a voltage for turning the second and third switching elements ON; and a first timing shift circuit connected between the gate of the third switching element and the second reference voltage sour

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: The invention in this application relates to a toner composition for electrostatic latent image development which is characterized in that, in a toner composition comprising at least binder resin, colorant and charge control agent, to be used in a print forming method provided with a print fixing device which fixes the toner image on a recording medium by means of a light flash, the concentration of benzene generated by heating for 90 seconds at 330° C. is no more than 60 &mgr;g/g, and the invention provides a toner composition for electrostatic latent image development which either extends the filter life or does not require the use of a filter.

Abstract: To suppress the power-on current flowing when power is tuned on in the circuit which feeds precharging current to the bit lines of the banks in a synchronous DRAM comprising a multi-bank structure. The device comprises a plurality of bank circuits BKi which are all of the same structure, wherein the bit line precharging power supply lines which the respective bank circuits have are connected in common, a first precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation when the power supply in the DRAM chip is turned on, and a second precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation after the bit line has been raised to a predetermined potential by the precharging current of the first precharging power supply circuit.