Patents by Inventor Takashi Taira

Takashi Taira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6081468
    Abstract: To suppress the power-on current flowing when power is tuned on in the circuit which feeds precharging current to the bit lines of the banks in a synchronous DRAM comprising a multi-bank structure. The device comprises a plurality of bank circuits BKi which are all of the same structure, wherein the bit line precharging power supply lines which the respective bank circuits have are connected in common, a first precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation when the power supply in the DRAM chip is turned on, and a second precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation after the bit line has been raised to a predetermined potential by the precharging current of the first precharging power supply circuit.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Taira, Kimimasa Imai
  • Patent number: 5831421
    Abstract: A semiconductor device includes an internal circuit and first and second supply voltage-lowering circuits in its semiconductor chip. The first supply voltage-lowering circuit steps down an external power supply potential of the semiconductor chip in response to a control signal, generates a first internal power supply potential, and supplies it to the internal circuit. The second supply voltage-lowering circuit steps down the external power supply potential of the semiconductor chip in response to the control signal, generates a second internal power supply potential of substantially the same level as that of the first internal power supply potential, and supplies it to the internal circuit. The first and second internal power supply potentials output from the first and second supply voltage-lowering circuits vary out of phase with each other to cancel out variations in first and second internal power supply potentials.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: November 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Taira, Kazuyoshi Muraoka
  • Patent number: 5521037
    Abstract: The present invention relates to an intermediate transfer material, used for an image forming method of developing an electrostatic latent image on an electrostatic latent image carrier utilizing a liquid toner, electrostatically transferring the image visualized by development onto an intermediate transfer material, and re-transferring visible image from the intermediate transfer material onto final transfer objects, utilizing as the intermediate transfer material at least a silicone rubber layer, an adhesive layer and a conductive fluorine rubber layer in this order from the outer surface side thereof.The intermediate transfer material of the present invention is excellent in durability and transferability, and so the image forming method using said intermediate transfer material can provide a high quality image at high reproducibility.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: May 28, 1996
    Assignee: Toray Industries, Inc.
    Inventors: Kimikazu Nagase, Takashi Taira, Sachio Suzuki, Hisayoshi Yamada