Patents by Inventor Takashi Taniguchi
Takashi Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5701762Abstract: Apparatus for recovering high-boiling point solvents which comprises: a honeycomb-structured rotor 1 having an adsorbent supported thereon; a separator 3 for partitioning the neighborhood of each end face of the rotor into two regions, adsorption zone 5 and desorption zone 4; fan means F.sub.1 that supplies the adsorption zone 5 with air containing a solvent boiling at 150.degree. to 300.degree. C. and which causes part of the clean gas effluent a from the opposite end face of the rotor to be released into the air atmosphere while the remainder is supplied into the desorption zone 4; heating means H for heating the clean gas; cooling means C for separating a solvent enriched gas S into a liquefied product L to be recovered and a cooled lean gas V; and return means F.sub.2 for turning the cooled lean gas V back to the feed gas.Type: GrantFiled: December 20, 1996Date of Patent: December 30, 1997Assignees: Nichias Corporation, Toho Chemical Engineering and Construction Co., Ltd.Inventors: Mikio Akamatsu, Kenji Seki, Katsuhiro Yamashita, Takeya Kobayashi, Takashi Taniguchi
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Patent number: 5633818Abstract: An apparatus uses a sticky digit in rounding an interim solution Yr into a final approximate solution Ye for an infinite precise solution Y, determined by a function F according to Y=F(X) with respect to digital data X. The apparatus includes a partial product generator receiving a multiplicand and a multiplier, at least one of which represents an interim solution Yr, for generating a plurality of partial products; a sign inversion generator for generating a sign inversion value, expressed in the same format as the partial products, from at least a lower part of a subtrahend to enable place matching, where the subtrahend represents the digital data X; an adder for adding the partial products and the sign inversion value; a detector which, in response to the addition result, detects whether the subtrahend or a product of the multiplicand and multiplier is greater; and a sticky digit generator for generating the sticky digit in response to the detection result.Type: GrantFiled: May 8, 1995Date of Patent: May 27, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Taniguchi
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Patent number: 5617049Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.Type: GrantFiled: July 31, 1995Date of Patent: April 1, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Takashi Taniguchi
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Patent number: 5612432Abstract: An optical sheetlike article possessing a glass transition point and a softening point both higher than 130.degree. C., a modulus of elasticity when bent of more than 50 kgf/mm.sup.2, a double refraction index not greater than 30 nm, a yellowness index of not greater than 5, a specific gravity of not more than 1.5, an amount of deflection of not more than 10 mm in a load flexure test, and a thickness of more than 0.3 mm and not more than 0.7 mm is provided, and is ideal for use in optical filters for display devices, substrates for liquid crystal display devices, substrates for optical recording discs, and optical lenses, among others.Type: GrantFiled: August 16, 1994Date of Patent: March 18, 1997Assignee: Toray Industries, Inc.Inventors: Takashi Taniguchi, Kazuo Tanaka, Shinya Adachi, Masaki Maekawa
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Patent number: 5584916Abstract: The present invention relates to an organic-solvent vapor adsorbing apparatus which includes a rotor containing an adsorbent and having tubular draft passages arranged in a direction of the rotational axis thereof. Plate-like separators disposed along a radial direction of the rotor define a plurality of zones. A treatment zone is provided for removing organic solvent vapor from a gaseous stream passed therethrough and into the adsorbent. A regeneration zone is also provided for removing the organic solvent from the adsorbent by a heated air stream passed therethrough. Finally, a purge zone is provided for cooling the adsorbent with cool air. Air exiting the purge zone is merged with the heated air stream which is introduced into the regeneration zone.Type: GrantFiled: September 8, 1994Date of Patent: December 17, 1996Assignee: Nichias CorporationInventors: Katsuhiro Yamashita, Takashi Taniguchi
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Patent number: 5559231Abstract: A spiro-oxazine compound represented by the following general formula (A) or (A') is a photochromic compound having an excellent fatigue resistance to repetition of coloration and decoloration and an abundance of hues: ##STR1## wherein the .alpha. ring is a ring selected from a 5-membered ring having one N atom, which may be connected to a benzene ring or naphthalene ring, and a 6-membered ring having one N atom, with the proviso that the N atom in the e ring is bonded to a C.sub.1-20 alkyl or another organic group, X is selected from O, S, Se and N-R.sup.1 (in which R.sup.1 is selected from H, and C.sub.1-20 alkyl and other organic groups), R.sup.2 and R.sup.3 are selected from --OH, amino, C.sub.1-20 alkoxy, halogen, and other groups, and k is an integer of 0 to 2.Type: GrantFiled: August 1, 1994Date of Patent: September 24, 1996Assignee: Toray Industries, Inc.Inventors: Shinichi Yamamoto, Takashi Taniguchi
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Patent number: 5555393Abstract: A method and an apparatus for cache lock control are designed for use with a cache memory. The cache memory has divided entries each for storing data and cache lock information. Updating of data in each of the entries of the cache memory is controlled in response to cache priority order information in each of the entries of the cache memory.Type: GrantFiled: October 27, 1995Date of Patent: September 10, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Tanaka, Takashi Taniguchi
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Patent number: 5518818Abstract: A primer comprising a polymer which comprises copolymerized units of an UV absorber having an unsaturated double bond, and a multilayer coated article comprising a substrate, a coating of the primer and a surface coating. The coatings of the multilayer coated article exhibit excellent weathering-resistant adhesion to a substrate, and they improve the surface properties thereof, such as surface hardness, scuff resistance, wear resistance and surface gloss. Accordingly, the coatings can impart excellent durability to the article and inhibit weathering deterioration of the substrate.Type: GrantFiled: October 4, 1993Date of Patent: May 21, 1996Assignee: Toray Industries, Inc.Inventors: Masayuki Kidai, Hiroko Fujimoto, Takashi Taniguchi
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Patent number: 5514466Abstract: A plastic optical article wherein a transparent coating film is applied on a transparent three-dimensional cross-linked resin having a glass transition temperature of at least 130.degree. C. The article has excellent heat resistance, solvent resistance, chemical resistance, abrasion resistance and transparency, and is used as optical materials for optical lenses and substrate materials for various display devices. Also when an inorganic thin film is deposited on a surface such as a transparent electro-conductive film, a thin film having a high heat resistance can be obtained.Type: GrantFiled: June 30, 1994Date of Patent: May 7, 1996Assignee: Toray Industries, Inc.Inventors: Shinichi Yamada, Naoki Shimoyama, Takashi Taniguchi, Syunzi Kono
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Patent number: 5513362Abstract: A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M.Type: GrantFiled: April 20, 1993Date of Patent: April 30, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Miki Urano, Takashi Taniguchi
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Patent number: 5495434Abstract: In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data derived is detected from the derived overflow signals.Type: GrantFiled: November 7, 1994Date of Patent: February 27, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Taniguchi
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Patent number: 5487162Abstract: A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.Type: GrantFiled: November 10, 1994Date of Patent: January 23, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Tanaka, Takashi Taniguchi
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Patent number: 5447798Abstract: A concrete article having a mixture layer comprising concrete and a polysulfide-modified epoxy resin as an intermediate layer between a concrete body and a cured layer of a polysulfide-modified epoxy resin, which concrete article is excellent in corrosion resistance, durability and workability, and shows good adhesion to the concrete body and to the cured layer of the polysulfide-modified epoxy resin. This concrete article can be produced by applying a coating composition containing the polysulfide-modified epoxy resin to the concrete body in an uncured state.Type: GrantFiled: June 22, 1993Date of Patent: September 5, 1995Assignees: Toray Industries, Inc., Toray Thiokol Co., Ltd.Inventors: Tadami Kamaishi, Hideaki Tanisugi, Keiichi Minami, Akio Takahashi, Takashi Taniguchi, Hiroyoshi Kuramoto
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Patent number: 5434809Abstract: An approximate square root Ya of a given value X is derived by referring to a relation Y=X.sup.1/2 at an accuracy at which an error between the approximate square root Ya and an infinitely precise square root Y is smaller than a weight of a digit in a digit place which is lower by two digit places than a least significant digit place for a final square root. The approximate square root Ya is rounded to an interim square root Yr equal to one of possible interim square roots which is closest to the approximate square root Ya. A value Xr is derived from the interim square root Yr using a relation Xr=Yr2. A sticky digit S is set to 0, 1, or -1 in response to a relation between the values X and Xr. The sticky digit S is added to a digit place having an order immediately lower than a lowest order digit place of the interim square root Yr, and a result of the addition is rounded in a designated rounding mode to obtain the final square root.Type: GrantFiled: March 29, 1994Date of Patent: July 18, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Taniguchi
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Patent number: 5418406Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.Type: GrantFiled: August 17, 1992Date of Patent: May 23, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Takashi Taniguchi
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Patent number: 5379244Abstract: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.Type: GrantFiled: September 23, 1993Date of Patent: January 3, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Miyoshi, Takashi Taniguchi
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Patent number: 5374723Abstract: A spiro-oxazine compound represented by the following general formula (A) or (A') is a photochromic compound having an excellent fatigue resistance to repetition of coloration and decoloration and an abundance of hues: ##STR1## wherein the .alpha. ring is a ring selected from a 5-membered ring having one N atom, which may be connected to a benzene ring or naphthalene ring, and a 6-membered ring having one N atom, with the proviso that the N atom in the .alpha.ring is bonded to a C.sub.1-20 alkyl or another organic group, X is selected from O, S, Se and N--R.sup.1 (in which R.sup.1 is selected from H, and C.sub.1-20 alkyl and other organic groups), R.sup.2 and R.sup.3 are selected from --OH, amino, C.sub.1-20 alkoxy, halogen, and other groups, and k is an integer of 0 to 2.Type: GrantFiled: March 29, 1993Date of Patent: December 20, 1994Assignee: Toray Industries, Inc.Inventors: Shinichi Yamamoto, Takashi Taniguchi
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Patent number: 5373459Abstract: In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data derived is detected from the derived overflow signals.Type: GrantFiled: April 17, 1992Date of Patent: December 13, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Taniguchi
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Patent number: 5317526Abstract: At a format conversion of a floating point number from double-precision to single-precision, a temporary exponent e.sub.1 is obtained by subtracting a double-precision bias B.sub.d from an exponent E of an operand and by adding a single-precision bias B.sub.s thereto. A mantissa M of the operand is shifted to right by a number obtained by adding 1 to an absolute value of the exponent e.sub.1 when e.sub.1 .ltoreq.0. When e.sub.1 >0, the mantissa M is not shifted. the result is rounded to a 23-bit length. When no carry is caused, the rounded value and 0 (when e.sub.1 .ltoreq.0) or e.sub.1 (when e.sub.1 >0) are respectively a mantissa and an exponent to be obtained. The rounded value and e.sub.1 +1 are regarded as a conversion result when e.sub.1 =0 and a carry is caused. A value obtained by shifting the rounded value to right by 1 bit and e.sub.1 +1 are selected when e.sub.1 >0 and a carry is caused.Type: GrantFiled: September 23, 1992Date of Patent: May 31, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Miki Urano, Takashi Taniguchi
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Patent number: 5313415Abstract: An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an infinitely precise solution Y is smaller than a weight of a digit in a place lower than a lowest place of significant digits for a final solution by two places. The approximate solution Ya is rounded to an interim solution Yr equal to one of possible interim solutions which is closest to the approximate solution Ya. A value Xr is derived from the interim solution Yr and an inverse function F.sup.-1 by referring to a relation Xr=F.sup.-1 (Yr). A sticky digit S is set to 0, 1, or -1 in response to the relation between the magnitudes of the values X and Xr and other information. The sticky digit S is added to a place immediately lower than a lowest place of the interim solution Yr. A result of this addition is rounded in a designated rounding mode to obtain the final solution.Type: GrantFiled: February 2, 1993Date of Patent: May 17, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Taniguchi