Abstract: An image capturing device comprising first and second solid image capturing elements each having a plurality of light receiving elements, a driving control circuit for controlling operation of the first and second solid image capturing elements, and a register for storing first and second setting data which respectively designate driving conditions for the first and second solid image capturing elements, wherein the driving control circuit drives the first solid image capturing element according to the first setting data and the second solid image capturing element according to the second setting data.

Abstract: A drive apparatus that guarantees the stable operation of a CCD image sensor. The drive apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The power supply circuit includes an over-boosting circuit for temporarily over-boosting the voltage supplied to the drive circuit to generate an over-boosted voltage, prior to the charge transfer operation of the CCD image sensor.

Abstract: An imaging device that is activated quickly and prevents deterioration of an image signal. The imaging device includes a boosting circuit for boosting an input voltage to generate a boosted voltage. A solid state imaging device receives the boosted voltage and generates the image signal. A clock signal generation unit is connected to the boosting circuit to determine a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit. The clock signal generation unit continuously generates the boosting clock signal during a predetermined period in which the imaging operation starts and, after the predetermined period, generates the boosting clock signal during at least part of a blanking period of the vertical synchronization signal and the horizontal synchronization signal.

Abstract: A booster for generating stable boosted voltage with respect to fluctuation of power supply voltage and load current. The booster has a charge pump circuit including a plurality of boosting units connected in series to selectively validate the boosting units and generate the boosted voltage in accordance with the number of validated boosting units. A boost control circuit is connected to the charge pump circuit to determine whether the boosted voltage is in a predetermined range and change the number of validated boosting units in accordance with the determination.

Abstract: A charge transfer device for transferring information charge packet in accordance with a vertical synchronization signal and a horizontal synchronization signal. The charge transfer device includes a capacitor for storing information charge packet. An output amplifier is connected to the capacitor to be supplied with and operated by a first voltage. The output amplifier receives the potential at the capacitor and generates an image signal corresponding to the potential at the capacitor. The supply of the first voltage to the output amplifier is stopped during a blanking period of the vertical and horizontal synchronization signals.

Abstract: A voltage boost system for smoothly converging an output voltage of a voltage booster when feedback controlling the output voltage. The voltage boost system includes a voltage booster to increase an input voltage and generate a boosted output voltage. A feedback control circuit is connected to the voltage booster to compare first and second voltages, which are based on either one of an output voltage of the voltage booster and a reference voltage, with a third voltage, which is based on the other one of the output voltage and the reference voltage. The feedback control circuit generates a feedback signal based on the comparison to feedback control the voltage booster. The feedback control circuit maintains the feedback signal at a constant value when the third voltage is included between the first and second voltages.

Abstract: A signal processor for reducing power consumption. The signal processor includes a signal processing circuit and an output circuit, which outputs an image signal generated by the signal processing circuit. The signal processor further includes a first regulator for generating a first regulated voltage from a power supply voltage and supplying the first regulated voltage to the signal processing circuit. A second regulator generates a second regulated voltage, which is greater than the first regulated voltage, from the power supply voltage and supplies the second regulated voltage to the output circuit.

Abstract: A signal processor for reducing power consumption. The signal processor includes a signal processing circuit and a first regulator connected to the signal processing circuit. The first regulator receives an external regulated voltage from an external regulator connected to the signal processor and generates an internal regulated voltage that is in accordance with an output level of a CCD image sensor. The signal processing circuit operates with the internal regulated voltage and performs a predetermined signal processing on an image signal generated by the CCD image sensor.

Abstract: An image signal processor for reducing power consumption. The image signal processor is connected between a solid-state imaging device, which generates a first image signal, and an external device, and includes first and second regulators, a switch circuit, a signal processing circuit, and an output circuit. The first regulator generates a first voltage that is in accordance with an output level of the solid-state imaging device. The second regulator generates a second voltage that is in accordance with an input level of the external device. The switch circuit supplies the power supply voltage or the second voltage to the output circuit in accordance with the operating state of the imaging external device. The signal processing circuit operates with the first voltage and generates a second image signal. The output circuit provides the second image signal to the external device.

Abstract: A signal processor for reducing power consumption. The signal processor includes a first regulator for generating a first regulated voltage with a power supply voltage and supplying the first regulated voltage to a signal processing circuit. A second regulator generates a second regulated voltage with the power supply voltage and supplies the second regulated voltage to an output circuit. The second regulator shifts the second regulated voltage in accordance with a change in an input level of the external device.

Abstract: An imaging apparatus for reducing power consumption. The apparatus includes a first regulator connected to a signal processing circuit and a second regulator connected to an output circuit. The first regulator generates a first regulated voltage that is in accordance with an output level of a solid-state image sensor. The second regulator generates a second regulated voltage that is in accordance with an input level of an external device.

Abstract: A voltage boost system for smoothly converging an output voltage of a voltage booster when feedback controlling the output voltage. The voltage boost system includes a voltage booster to increase an input voltage and generate a boosted output voltage. A feedback control circuit is connected to the voltage booster to compare first and second voltages, which are based on either one of an output voltage of the voltage booster and a reference voltage, with a third voltage, which is based on the other one of the output voltage and the reference voltage. The feedback control circuit generates a feedback signal based on the comparison to feedback control the voltage booster. The feedback control circuit maintains the feedback signal at a constant value when the third voltage is included between the first and second voltages.

Abstract: A voltage boost system that prevents power consumption from increasing. The voltage boost system has a load device including a high potential power supply terminal and a low potential power supply terminal. A power supply generates a first potential by that is greater than a ground potential. A voltage booster is connected to the power supply to increase the first potential and generate a second potential that is greater than the first potential. The second potential of the voltage booster is provided to the high potential power supply terminal of the load device, and the first potential of the power supply is provided to the low potential power supply terminal of the load device.

Abstract: A drive apparatus that guarantees the stable operation of a CCD image sensor. The drive apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The power supply circuit includes an over-boosting circuit for temporarily over-boosting the voltage supplied to the drive circuit to generate an over-boosted voltage, prior to the charge transfer operation of the CCOD image sensor.

Abstract: A charge pump circuit for converting an input voltage to a predetermined voltage. The charge pump circuit includes switching transistors, which are connected in series between an output terminal and reference potential terminal of the charge pump circuit, and a capacitor connected to a node between the first and second transistors. The switching transistors include a first transistor connected to the reference potential terminal and a second transistor connected to the first transistor. The capacitor has a first terminal connected to a node between the transistors and a second terminal connected to a delay circuit. The delay circuit is connected between the second terminal of the capacitor and a control terminal of the first transistor. The delay circuit delays a clock signal received by the control terminal by a predetermined time and provides the delayed first clock signal to the second terminal of the capacitor.

Abstract: An apparatus for optically reading a code pattern, made up of numerous code elements, if provided. The apparatus includes a light receiving unit, a photometer and a controller. The light receiving unit includes a plurality of first pixels, charge transfer section and a first charge converting section. The photometer includes a second pixel and a second charge converting section. The controller includes a comparator for comparing a second signal voltage to a predetermined voltage level and a clock generator for supplying a drive clock signal to the charge transfer section when the second signal voltage is greater than the predetermined voltage level. An apparatus for optically reading a combined code pattern which includes information and reference code patterns each made up of first and second code elements which are alternately mixed, is provided. The apparatus for reading a combined code pattern includes a light receiving unit, first and second sample and hold circuits and a binarizing circuit.

Abstract: An apparatus for optically reading a code pattern, made up of numerous code elements, if provided. The apparatus includes a light receiving unit, a photometer and a controller. The light receiving unit includes a plurality of first pixels, charge transfer section and a first charge converting section. The photometer includes a second pixel and a second charge converting section. The controller includes a comparator for comparing a second signal voltage to a predetermined voltage level and a clock generator for supplying a drive clock signal to the charge transfer section when the second signal voltage is greater than the predetermined voltage level. An apparatus for optically reading a combined code pattern which includes information and reference code patterns each made up of first and second code elements which are alternately mixed, is provided. The apparatus for reading a combined code pattern includes a light receiving unit, first and second sample and hold circuits and a binarizing circuit.