Patents by Inventor Takashi Togasaki

Takashi Togasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180264513
    Abstract: In one embodiment, a liquid discharge head includes, a circuit board including a drive IC, and a circulation flow path including a supply flow path that communicates with a liquid discharge unit that discharges liquid, and a collection flow path that is provided in a manner so that heat is transmittable to the circuit board, the collection flow path that communicates with the liquid discharge unit.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 20, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi TOGASAKI, Kumiko IOKA, Takahiro AIZAWA, Michinobu INOUE
  • Publication number: 20170170150
    Abstract: A semiconductor module according to an embodiment has first and second wiring portions, first semiconductor devices and second semiconductor devices. The second wiring portion is provided to oppose the first wiring portion. The third wiring portion is provided to oppose the first wiring portion. The first semiconductor devices are provided between the first wiring portion and the second wiring portion. Each of the first semiconductor devices has a first switching element, and an input terminal or an output terminal of the first switching element is electrically connected with the first wiring portion. The second semiconductor devices are provided between the first wiring portion and the third wiring portion. Each of the second semiconductor devices has a second switching element, and an output or input terminal of the second switching element is electrically connected with the first wiring portion in a manner contrary to the first switching element.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 15, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro IGUCHI, Akihiro Sasaki, Tetsuya Yamamoto, Takashi Togasaki
  • Patent number: 9147673
    Abstract: According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Nishiuchi, Kazuhiro Ueda, Takayuki Masunaga, Naotake Watanabe, Yoshiyuki Shimizu, Takashi Togasaki, Koji Maruno
  • Publication number: 20150270203
    Abstract: According to one embodiment, a first semiconductor element has a first electrode connected to the first conductor, a second electrode connected to the second conductor, and a control electrode connected to a first signal terminal. A second semiconductor element has a first electrode connected to the first conductor, and a second electrode connected to the second conductor. A third semiconductor element has a first electrode connected to the third conductor, a second electrode connected to the fourth conductor, and a control electrode connected to a second signal terminal. A fourth semiconductor element has a first electrode connected to the third conductor, and a second electrode connected to the fourth conductor.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideo NISHIUCHI, Takashi TOGASAKI, Takayuki TAJIMA
  • Patent number: 8872327
    Abstract: According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Masunaga, Kazuhiro Ueda, Naotake Watanabe, Yoshiyuki Shimizu, Hideo Nishiuchi, Takashi Togasaki, Satoshi Sayama
  • Publication number: 20140124909
    Abstract: According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line.
    Type: Application
    Filed: September 12, 2013
    Publication date: May 8, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Masunaga, Kazuhiro Ueda, Naotake Watanabe, Yoshiyuki Shimizu, Hideo Nishiuchi, Takashi Togasaki, Satoshi Sayama
  • Publication number: 20140117526
    Abstract: According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed.
    Type: Application
    Filed: September 12, 2013
    Publication date: May 1, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideo Nishiuchi, Kazuhiro Ueda, Takayuki Masunaga, Naotake Watanabe, Yoshiyuki Shimizu, Takashi Togasaki, Koji Maruno
  • Patent number: 8703600
    Abstract: An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Takashi Togasaki
  • Publication number: 20140103782
    Abstract: An aspect of one embodiment, there is provided an ultrasonic transducer including a plurality of oscillators, each of the oscillator having a convex portion, a printed wiring board provided to be opposed to the convex portion and electrically connected to the convex portion, a resin provided between the oscillator and the printed wiring board, the resin covering at least the convex portion and a portion of the printed wiring board.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi TOGASAKI, Takeshi Miyagi, Satoru Asagiri, Michiko Ooishi
  • Patent number: 8674587
    Abstract: An aspect of one embodiment, there is provided an ultrasonic transducer including a plurality of oscillators, each of the oscillator having a convex portion, a printed wiring board provided to be opposed to the convex portion, an adhesive material including at least a portion of the convex portion, the adhesive material joining the oscillator and the printed wiring board, and a resin provided between the oscillator and the printed wiring board, the resin covering the convex portion and the adhesive material.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Togasaki, Takeshi Miyagi, Satoru Asagiri, Michiko Ooishi
  • Patent number: 8653651
    Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Uchida, Takashi Togasaki, Satoru Hara, Kentaro Suga
  • Patent number: 8647280
    Abstract: An ultrasonic probe includes, a transducer, a substrate includes electrodes formed on a front surface and a back surface and electronic components, first flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the front surface of the substrate, second flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the back surface of the substrate, and a dummy materials including the same rigidity and thickness as those of the first flexible wire substrate is arranged at a space, adjacent to a electrode at the side of the front surface of the substrate, corresponding to the second end of the second flexible wire substrate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiko Ooishi, Satoru Asagiri, Takashi Togasaki, Takeshi Miyagi
  • Patent number: 8569181
    Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Tadashi Iijima, Takashi Togasaki
  • Publication number: 20130043594
    Abstract: According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yo Sasaki, Atsushi Yamamoto, Kazuya Kodani, Yuji Hisazato, Takashi Togasaki, Hideaki Kitazawa
  • Patent number: 8314491
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: November 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Yamashita, Tatsuo Migita, Tadashi Iijima, Masahiro Miyata, Masayuki Uchida, Takashi Togasaki, Hirokazu Ezawa
  • Publication number: 20120245470
    Abstract: An ultrasonic probe includes, a transducer, a substrate includes electrodes formed on a front surface and a back surface and electronic components, first flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the front surface of the substrate, second flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the back surface of the substrate, and a dummy materials including the same rigidity and thickness as those of the first flexible wire substrate is arranged at a space, adjacent to a electrode at the side of the front surface of the substrate, corresponding to the second end of the second flexible wire substrate.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 27, 2012
    Inventors: Michiko Ooishi, Satoru Asagiri, Takashi Togasaki, Takeshi Miyagi
  • Publication number: 20120235291
    Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 20, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki UCHIDA, Takashi TOGASAKI, Satoru HARA, Kentaro SUGA
  • Publication number: 20120028463
    Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Tadashi Iijima, Takashi Togasaki
  • Publication number: 20110316387
    Abstract: An aspect of one embodiment, there is provided an ultrasonic transducer including a plurality of oscillators, each of the oscillator having a convex portion, a printed wiring board provided to be opposed to the convex portion, an adhesive material including at least a portion of the convex portion, the adhesive material joining the oscillator and the printed wiring board, and a resin provided between the oscillator and the printed wiring board, the resin covering the convex portion and the adhesive material.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 29, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi TOGASAKI, Takeshi Miyagi, Satoru Asagiri, Michiko Ooishi
  • Patent number: 8063487
    Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Tadashi Iijima, Takashi Togasaki