Patents by Inventor Takashi Uehara
Takashi Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8577241Abstract: An image forming apparatus which is capable of reducing the number of times a second member is separated from a first member upon entry into power-save mode, thereby minimizing failures of a separation unit. A pressure-roller separating mechanism is provided so as to abut and separate a pressure roller and a fixing roller against/from each other. The image forming apparatus is controlled to change to a power-save mode in which power consumption of the image forming apparatus is reduced. The pressure-roller separating mechanism is controlled to separate the pressure roller and the fixing roller from each other in the power-save mode based on a measurement result measured by a timer, and the power-save mode is maintained after the pressure roller and the fixing roller are separated from each other.Type: GrantFiled: August 27, 2008Date of Patent: November 5, 2013Assignee: Canon Kabushiki KaishaInventor: Takashi Uehara
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Publication number: 20120229368Abstract: A display includes a first optical effect layer including a first interface part, the first interface part being provided with recesses or protrusions arranged two-dimensionally at the minimum center-to-center distance of 200 nm to 500 nm, each of the recesses or protrusions having a forward-tapered shape, a reflective material layer covering at least a part of the first interface part, and a second optical effect layer including, at a position of a first portion of the first interface part that is covered with the reflective material layer, a portion that faces the reflective material layer with the first optical effect layer interposed therebetween or faces the first optical effect layer with the reflective material layer interposed therebetween, the second optical effect layer containing at least one of a cholesteric liquid crystal, a pearl pigment and a multilayer interference film.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Applicant: Toppan Printing Co., Ltd.Inventors: Manabu Watanabe, Mihoko Nagayoshi, Takashi Uehara, Hideki Ochiai
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Publication number: 20090060558Abstract: An image forming apparatus which is capable of reducing the number of times a second member is separated from a first member upon entry into power-save mode, thereby minimizing failures of a separation unit. A pressure-roller separating mechanism is provided so as to abut and separate a pressure roller and a fixing roller against/from each other. The image forming apparatus is controlled to change to a power-save mode in which power consumption of the image forming apparatus is reduced. The pressure-roller separating mechanism is controlled to separate the pressure roller and the fixing roller from each other in the power-save mode based on a measurement result measured by a timer, and the power-save mode is maintained after the pressure roller and the fixing roller are separated from each other.Type: ApplicationFiled: August 27, 2008Publication date: March 5, 2009Applicant: CANON KABUSHIKI KAISHAInventor: Takashi Uehara
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Patent number: 7426152Abstract: A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.Type: GrantFiled: July 18, 2007Date of Patent: September 16, 2008Assignee: Renesas Technology Corp.Inventors: Masahiro Yamashita, Takashi Uehara, Mamoru Takaku, Hiroaki Nambu
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Publication number: 20070274139Abstract: A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.Type: ApplicationFiled: July 18, 2007Publication date: November 29, 2007Inventors: Masahiro Yamashita, Takashi Uehara, Mamoru Takaku, Hiroaki Nambu
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Patent number: 7271701Abstract: A system for commonly utilizing a vehicle in which illegal use of the vehicle can be surely prevented. In the system for lending a shared vehicle, which is parked in a parking area and of which the use information concerning lending and returning is managed, to a user after confirming permission to utilize the vehicle based on previously registered personal identification information, the shared vehicle is provided in the control section thereof with a popup key which can control whether a mechanical switch unit for starting the driving of the vehicle can be operated or not, and with an ignition mechanism control mean which permits starting operation of an ignition mechanism when personal cipher information inputted by the user matches personal cipher information imparted to the user in association with the personal identification information and the user sets a destination, and permits returning operation of the ignition mechanism when arrival at the set destination is detected.Type: GrantFiled: July 25, 2002Date of Patent: September 18, 2007Assignee: Honda Motor Co., Ltd.Inventors: Mamoru Kokubu, Takashi Uehara, Yuji Uehara, Shunsuke Hayase
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Patent number: 7269086Abstract: A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.Type: GrantFiled: March 29, 2006Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Masahiro Yamashita, Takashi Uehara, Mamoru Takaku, Hiroaki Nambu
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Patent number: 7126174Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: November 24, 2004Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20060221727Abstract: A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.Type: ApplicationFiled: March 29, 2006Publication date: October 5, 2006Inventors: Masahiro Yamashita, Takashi Uehara, Mamoru Takaku, Hiroaki Nambu
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Patent number: 6967409Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6965323Abstract: In a motor vehicle sharing system for managing motor vehicles parked in a parking area and renting the motor vehicles to users, the motor vehicle is provided with a detector for detecting the start and end of motor vehicle rental, and a usage data measuring section for starting and completing measurements for motor vehicle usage data. The detector contains a position detector for detecting the parking area. The motor vehicle is further provided with a membership list in which user information is recorded, a charge list, a rentability judging section for judging whether the motor vehicle is rentable, and a charging data generating section for making charging data by referring to the motor vehicle usage data measured by the usage data measuring section and the charge list Thus, it is possible to perform the rental and return operation without relying on a control center.Type: GrantFiled: March 20, 2002Date of Patent: November 15, 2005Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Takashi Uehara, Tomohide Shimizu, Hiroshi Hamano, Mamoru Kokubu, Yuji Uehara, Shunsuke Hayase, Michio Fujinuma
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Patent number: 6962853Abstract: A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.Type: GrantFiled: January 7, 2003Date of Patent: November 8, 2005Assignee: Matsushita Electronic Industrial Co., Ltd.Inventors: Mizuki Segawa, Takashi Uehara
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Publication number: 20050156220Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: March 17, 2005Publication date: July 21, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6890817Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.Type: GrantFiled: August 5, 2003Date of Patent: May 10, 2005Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Maeda, Toshiyuki Oashi, Takashi Uehara
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Publication number: 20050093089Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: November 24, 2004Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20050080752Abstract: In a motor vehicle sharing system for managing motor vehicles are parked in a parking area and renting the motor vehicles to users, the motor vehicle is provided with a detector for detecting a start of motor vehicle rental and end of the motor vehicle rental, and an usage data measuring section for starting a measurement for a motor vehicle usage data when the detector detects a start of the motor vehicle rental and completing the measurement for the motor vehicle usage data when the detector detects an end of the motor vehicle rental. The detector contains a position detector for detecting the parking area.Type: ApplicationFiled: March 20, 2002Publication date: April 14, 2005Inventors: Takashi Uehara, Tomohide Shimizu, Hiroshi Hamano, Mamoru Kokubu, Yuji Uehara, Shunsuke Hayase, Michio Fujinuma
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Patent number: 6847119Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20050012589Abstract: A system for commonly utilizing a vehicle in which illegal use of the vehicle can be surely prevented. In the system for lending a shared vehicle, which is parked in a parking area and of which the use information concerning lending and returning is managed, to a user after confirming permission to utilize the vehicle based on previously registered personal identification information, the shared vehicle is provided in the control section thereof with a popup key which can control whether a mechanical switch unit for starting the driving of the vehicle can be operated or not, and with an ignition mechanism control mean which permits starting operation of an ignition mechanism when personal cipher information inputted by the user matches personal cipher information imparted to the user in association with the personal identification information and the user sets a destination, and permits returning operation of the ignition mechanism when arrival at the set destination is detected.Type: ApplicationFiled: July 25, 2002Publication date: January 20, 2005Inventors: Mamoru Kokubu, Takashi Uehara, Yuji Uehara, Shunsuke Hayase
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Patent number: 6835971Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.Type: GrantFiled: January 31, 2003Date of Patent: December 28, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara
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Patent number: 6770517Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.Type: GrantFiled: December 28, 2001Date of Patent: August 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Nakaoka, Hiromasa Fujimoto, Atsushi Hori, Takashi Uehara, Takehiro Hirai