Patents by Inventor Takashi Uehara
Takashi Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010054741Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: July 11, 2001Publication date: December 27, 2001Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.,LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20010020707Abstract: A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.Type: ApplicationFiled: January 16, 2001Publication date: September 13, 2001Inventors: Mizuki Segawa, Takashi Uehara
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Patent number: 6281562Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: July 24, 1996Date of Patent: August 28, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6143626Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.Type: GrantFiled: June 11, 1999Date of Patent: November 7, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Takashi Nakabayashi
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Patent number: 6124160Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.Type: GrantFiled: November 17, 1998Date of Patent: September 26, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
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Patent number: 6118738Abstract: The present invention provides a disk storage device capable of storing a plurality of types of disks, or a plurality of disks of the same type, and managing these disks easily to improve the operability of the apparatus. The invention reproduces the contents of the disks at high continuity even as disks of different types are exchanged. In order to manage disks stored in the disk storage device efficiently, there is provided the disk manager information memory device having the memory unit, in which the disk storage location data, disk type data and control data necessary for reproducing each disk are pre-stored together with additional data for managing each disk. When the additional data of a disk is input from an outside source, the management additional data which matches with the input additional data is searched, and the disk storage location data, data type data and control data, associated with the input additional data are read from the memory unit of the disk manager to be searched.Type: GrantFiled: May 8, 1998Date of Patent: September 12, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Uehara
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Patent number: 6108445Abstract: An input device including a display unit for displaying thereon characters entered from a keyboard or by a pen inputting operation, a character selector including a tablet for selecting any character from among the characters displayed on the display unit, and a CPU for receiving the characters selected by the character selector as a new input. When any character is selected from an already input character string displayed on the display unit, the selected character is added as a new character input to the already input characters, and displayed together on the display unit.Type: GrantFiled: July 14, 1997Date of Patent: August 22, 2000Assignee: Casio Computer Co., Ltd.Inventor: Takashi Uehara
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Patent number: 6069055Abstract: The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.Type: GrantFiled: July 1, 1997Date of Patent: May 30, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaaki Ukeda, Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Masatoshi Arai, Masaru Moriwaki
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Patent number: 6034416Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.Type: GrantFiled: April 16, 1998Date of Patent: March 7, 2000Assignee: Matsushita Electirc Industrial Co., Ltd.Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takaaki Ukeda, Masatoshi Arai, Masaru Moriwaki
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Patent number: 5986313Abstract: There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed.Type: GrantFiled: December 11, 1997Date of Patent: November 16, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Ueda, Takashi Uehara, Kousaku Yano, Satoshi Ueda
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Patent number: 5960300Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.Type: GrantFiled: December 19, 1995Date of Patent: September 28, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Takashi Nakabayashi
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Patent number: 5946563Abstract: There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.Type: GrantFiled: June 23, 1997Date of Patent: August 31, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takashi Nakabayashi, Minoru Fujii
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Patent number: 5879983Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.Type: GrantFiled: September 18, 1996Date of Patent: March 9, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
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Patent number: 5844801Abstract: After outer panels have been assembled on a vehicle frame, they are coated with an aqueous lustering agent P, and then irradiated with a light beam L. Light reflected by the outer panels is processed to produce a degree and range of distortion thereof. Based on the produced degree and range of distortion, it is determined whether the outer panels suffer a surface distortion or not. The determined result is displayed on a display monitor. According to the displayed image, the outer panels are repaired and thereafter coated with a paint.Type: GrantFiled: September 20, 1995Date of Patent: December 1, 1998Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Akira Kodama, Yasuhiko Kitano, Hiroya Miyaoka, Hisato Morita, Takashi Uehara, Hideaki Maruyama, Tadatoshi Tsuji, Nobuhiro Nagao, Yoshikazu Kaizu
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Patent number: 5756382Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.Type: GrantFiled: January 23, 1997Date of Patent: May 26, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Yoshiaki Kato, Hiroaki Nakaoka, Takashi Nakabayashi, Atsushi Hori, Hiroshi Masuda, Ichiro Matsuo, Akihira Shinohara, Takashi Uehara, Mitsuo Yasuhira
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Patent number: 5736421Abstract: Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).Type: GrantFiled: January 23, 1996Date of Patent: April 7, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Shimomura, Kiyoyuki Morita, Takashi Nakabayashi, Takashi Uehara, Mitsuo Yasuhira, Mizuki Segawa, Takehiro Hirai
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Patent number: 5733812Abstract: There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed.Type: GrantFiled: December 12, 1995Date of Patent: March 31, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Ueda, Takashi Uehara, Kousaku Yano, Satoshi Ueda
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Patent number: 5726071Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.Type: GrantFiled: January 23, 1997Date of Patent: March 10, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Yoshiaki Kato, Hiroaki Nakaoka, Takashi Nakabayashi, Atsushi Hori, Hiroshi Masuda, Ichiro Matsuo, Akihira Shinohara, Takashi Uehara, Mitsuo Yasuhira
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Patent number: 5698902Abstract: There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.Type: GrantFiled: December 18, 1995Date of Patent: December 16, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takashi Nakabayashi, Minoru Fujii
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Patent number: 5686340Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.Type: GrantFiled: September 30, 1996Date of Patent: November 11, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Yoshiaki Kato, Hiroaki Nakaoka, Takashi Nakabayashi, Atsushi Hori, Hiroshi Masuda, Ichiro Matsuo, Akihira Shinohara, Takashi Uehara, Mitsuo Yasuhira