Patents by Inventor Takashi Yoneda
Takashi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080292792Abstract: A novel azo compound represented by the following formula (1) wherein A represents the following formula (2) and is located preferably in a position meta or para to the azo group; R1 and R2 each independently represents hydrogen, carboxy, sulfo, nitro, C1-4 alkoxy, etc.; R3 and R4 each independently represents hydrogen, halogeno, cyano, carboxy, sulfo, nitro, C1-4 alkyl, hydroxy, or C1-4 alkoxy; and n is 0 or 1. [In the formula (2), R5 represents cyano, carboxy, C1-4 alky, C1-4 alkoxycarbonyl, or phenyl; and R6, R7, and R8 each independently represents hydrogen, halogeno, cyano, carboxy, sulfo, nitro, C1-4 alkyl, C1-4 alkoxy, or acylamino.] The compound is useful as a black dye, especially one for ink compositions for, e.g., ink-jet prints. Also provided are: an ink composition which contains the compound and has excellent storage stability; and a print obtained through recording with the ink. The print is excellent in light resistance, ozone resistance, fastness to moisture, etc.Type: ApplicationFiled: April 6, 2005Publication date: November 27, 2008Inventors: Takahiko Matsui, Hiroaki Ohno, Takashi Yoneda, Yasuo Shirasaki
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Patent number: 7427319Abstract: The present invention relates to an azo compound represented by the following formula (1): (wherein, in the formula (1), R1 represents a hydrogen atom; a hydroxyl group; a carboxyl group; a (C1-C4)alkyl group which may be substituted by a hydroxyl group or a (C1-C4)alkoxy group; or the like, and A represents an aliphatic amine residue having a carboxyl group or a sulfo group, respectively;) or a salt thereof; an ink composition containing the same; and an inkjet recording method and a colored object using the same. Said azo compound has a high color value and has a hue between yellow and red or a brown hue. The ink containing said azo compound has satisfactory storage stability, and exhibits, when printed therewith, a stable ejection property even on a thermal type inkjet printer, and gives a print of high quality (superior in light fastness, ozone gas fastness and moisture fastness).Type: GrantFiled: June 21, 2005Date of Patent: September 23, 2008Assignee: Nippon Kayaku Kabushiki KaishaInventors: Takashi Yoneda, Hiroaki Ohno, Yasuo Shirasaki
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Patent number: 7326288Abstract: [PROBLEMS] To provide: a black compound which is for use in ink-jet recording or writing utensils, is excellent in ozone resistance, light resistance, moisture resistance, and color rendering, and gives a recording fluid having satisfactory storage stability; and an ink composition containing the compound. [MEANS FOR SOLVING PROBLEMS] The black compound is a trisazo compound represented by the following formula (1) or a salt thereof. (1) [In the formula (1), R1 and R2 each independently represents hydrogen, carboxy, sulfo, hydroxy, a C1-4 alkyl, C1-4 alkoxy, or sulfo group optionally substituted by C1-4 alkoxy, an optionally carboxylated C1-4 alkoxy group, etc.; and A represents phenyl or naphthyl (provided that the phenyl and naphthyl groups may be substituted by halogeno, carboxy, sulfo, sulfamonyl optionally substituted by alkyl or phenyl, nitro, etc.).Type: GrantFiled: November 26, 2004Date of Patent: February 5, 2008Assignee: Nippon Kayaku Kabushiki KaishaInventors: Takahiko Matsui, Hiroaki Ohno, Takashi Yoneda, Yoshiaki Kawaida, Yasuo Shirasaki
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Publication number: 20070257975Abstract: The present invention relates to an azo compound represented by the following formula (1): (wherein, in the formula (1), R1 represents a hydrogen atom; a hydroxyl group; a carboxyl group; a (C1-C4)alkyl group which may be substituted by a hydroxyl group or a (C1-C4)alkoxy group; or the like, and A represents an aliphatic amine residue having a carboxyl group or a sulfo group, respectively;) or a salt thereof; an ink composition containing the same; and an inkjet recording method and a colored object using the same. Said azo compound has a high color value and has a hue between yellow and red or a brown hue. The ink containing said azo compound has satisfactory storage stability, and exhibits, when printed therewith, a stable ejection property even on a thermal type inkjet printer, and gives a print of high quality (superior in light fastness, ozone gas fastness and moisture fastness).Type: ApplicationFiled: June 21, 2005Publication date: November 8, 2007Inventors: Takashi Yoneda, Hiroaki Ohno, Yasuo Shirasaki
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Patent number: 7288979Abstract: There is provided a semiconductor integrated circuit in which a source clock (S101) is inputted to a delay circuit (3), a counter circuit (6) is operated in response to a delay clock (S102) which is the output of the delay circuit (3), a clock used as a system clock by an internal circuit (4) is selected from the source clock (S101) and the delay clock (S102) based on the value of the counter circuit (6), and the duty cycle of the system clock is changed, so that it is possible to reduce electromagnetic interference resulting from harmonics generated by the switching of the internal circuit.Type: GrantFiled: July 14, 2005Date of Patent: October 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Yoneda
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Publication number: 20070227388Abstract: The present invention relates to black coloring matter, and relates to a compound represented by the following formula (1): (wherein A and D independently represent an optionally substituted phenyl group or naphthyl group, respectively, and m and n represent 1 or 2, respectively), and the coloring matter for recording and an ink comprising the same. Said compound exhibits high solubility in a medium containing water as a main component, is stable even when an aqueous dye solution or an ink having a high concentration is prepared therefrom and is stored for a long period of time, has low color rendering property, exhibits colorless and neutral black, provides a printed image having high density and also provides a black recorded image being excellent in moisture fastness, light fastness and an ozone gas fastness, and further can be synthesized easily and can be produced at a low cost.Type: ApplicationFiled: May 9, 2005Publication date: October 4, 2007Inventors: Hiroaki Ohno, Takahiko Matsui, Takashi Yoneda, Yasuo Shirasaki, Yoshiaki Kawaida
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Patent number: 7257789Abstract: An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.Type: GrantFiled: December 20, 2004Date of Patent: August 14, 2007Assignee: Fujitsu LimitedInventors: Toshikatsu Hosono, Takashi Yoneda
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Publication number: 20070127178Abstract: A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.Type: ApplicationFiled: December 1, 2006Publication date: June 7, 2007Inventor: Takashi Yoneda
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Publication number: 20070107628Abstract: [PROBLEMS] To provide: a black compound which is for use in ink-jet recording or writing utensils, is excellent in ozone resistance, light resistance, moisture resistance, and color rendering, and gives a recording fluid having satisfactory storage stability; and an ink composition containing the compound. [MEANS FOR SOLVING PROBLEMS] The black compound is a trisazo compound represented by the following formula (1) or a salt thereof. (1) [In the formula (1), R1 and R2 each independently represents hydrogen, carboxy, sulfo, hydroxy, a C1-4 alkyl, C1-4 alkoxy, or sulfo group optionally substituted by C1-4 alkoxy, an optionally carboxylated C1-4 alkoxy group, etc.; and A represents phenyl or naphthyl (provided that the phenyl and naphthyl groups may be substituted by halogeno, carboxy, sulfo, sulfamonyl optionally substituted by alkyl or phenyl, nitro, etc.).Type: ApplicationFiled: November 26, 2004Publication date: May 17, 2007Inventors: Takahiko Matsui, Hiroaki Ohno, Takashi Yoneda, Yoshiaki Kawaida, Yasuo Shirasaki
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Patent number: 7219320Abstract: OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.Type: GrantFiled: March 24, 2004Date of Patent: May 15, 2007Assignee: Fujitsu LimitedInventors: Tetsuo Kawano, Satoru Yoshikawa, Toshikatsu Hosono, Shigenori Ichinose, Takashi Yoneda
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Publication number: 20070106967Abstract: A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.Type: ApplicationFiled: April 4, 2006Publication date: May 10, 2007Applicant: FUJITSU LIMITEDInventors: Yoshio Inoue, Takashi Yoneda, Masaru Ito
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Publication number: 20070106966Abstract: A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.Type: ApplicationFiled: March 27, 2006Publication date: May 10, 2007Applicant: FUJITSU LIMITEDInventors: Yoshio Inoue, Takashi Yoneda, Masaru Ito
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Patent number: 7159200Abstract: A duty of a system clock is changed by a duty changing circuit, and a phase difference is provided between a current consumed at a leading edge of the system clock and a current consumed at a trailing edge thereof in an internal circuit, so as to shift phases of consumed currents away from each other. Thereby, frequency components concentrating on frequencies each of an even order frequency of the system clock can be cancelled and harmonic components each of a frequency of an even order in a current be reduced. Thus, a semiconductor equipment with less electromagnetic interference can be realized.Type: GrantFiled: July 12, 2004Date of Patent: January 2, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Yoneda
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Patent number: 7103738Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.Type: GrantFiled: August 26, 2003Date of Patent: September 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Yoneda, Tsutomu Kamiyoshi, Hiroshi Benno, Shirou Yoshioka, Tsuneo Uenishi
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Publication number: 20060144288Abstract: The present invention relates to a water-based black ink composition comprising a water-soluble black dye (A) exhibiting ozone fastness and a condensate compound (B) of 4,4?-dinitrostilbene-2,2?-disulfonic acid and aminobenzenes or a reduction product (C) thereof. Said ink composition is suitable for use in ink-jet recording, and realizes neutral hue and black color of high printing density. Further, a printed matter obtained is excellent in ozone gas fastness, light fastness, moisture fastness and color rendering properties. Still further, storage stability as a recording liquid is excellent.Type: ApplicationFiled: March 4, 2004Publication date: July 6, 2006Inventors: Hiroaki Ohno, Toru Yamaguchi, Takahiko Matsui, Takashi Yoneda, Yoshiaki Kawaida, Yasuo Shirasaki, Kazunobu Nagasaki
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Publication number: 20060017487Abstract: There is provided a semiconductor integrated circuit in which a source clock (S101) is inputted to a delay circuit (3), a counter circuit (6) is operated in response to a delay clock (S102) which is the output of the delay circuit (3), a clock used as a system clock by an internal circuit (4) is selected from the source clock (S101) and the delay clock (S102) based on the value of the counter circuit (6), and the duty cycle of the system clock is changed, so that it is possible to reduce electromagnetic interference resulting from harmonics generated by the switching of the internal circuit.Type: ApplicationFiled: July 14, 2005Publication date: January 26, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Takashi Yoneda
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Patent number: 6983402Abstract: In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.Type: GrantFiled: December 10, 2001Date of Patent: January 3, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Yoneda, Masahiko Matsumoto
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Publication number: 20050278672Abstract: An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.Type: ApplicationFiled: December 20, 2004Publication date: December 15, 2005Applicant: FUJITSU LIMITEDInventors: Toshikatsu Hosono, Takashi Yoneda
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Publication number: 20050081171Abstract: OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.Type: ApplicationFiled: March 24, 2004Publication date: April 14, 2005Applicant: FUJITSU LIMITEDInventors: Tetsuo Kawano, Satoru Yoshikawa, Toshikatsu Hosono, Shigenori Ichinose, Takashi Yoneda
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Publication number: 20050028149Abstract: There are provided in a compiler (2) a loop detecting part (6) that detects a loop portion from an intermediate code generated from a source program; a loop program formatting part (7) that generates a loop processing program for the loop portion when the loop detecting part (6) detects the loop portion; and, as a loop process changing part that changes the number of instruction steps required for performing the loop processing program generated by the loop program formatting part (7), a nop instruction adding part (11) that changes the loop processing program into a program to which n nop instructions are added.Type: ApplicationFiled: July 27, 2004Publication date: February 3, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Takita, Takashi Yoneda