Patents by Inventor Takashi Yoshitomi
Takashi Yoshitomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6894331Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.Type: GrantFiled: December 13, 2000Date of Patent: May 17, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Tatsuya Ohguro, Ryoji Hasumi, Hideki Kimijima, Takashi Yamaguchi, Masahiro Inohara
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Patent number: 6864137Abstract: A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.Type: GrantFiled: July 15, 2003Date of Patent: March 8, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Yuichi Nakashima
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Publication number: 20050001255Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.Type: ApplicationFiled: July 30, 2004Publication date: January 6, 2005Inventors: Takashi Yoshitomi, Tatsuya Ohguro, Ryoji Hasumi, Hideki Kimijima, Takashi Yamaguchi, Masahiro Inohara
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Publication number: 20040188747Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.Type: ApplicationFiled: April 13, 2004Publication date: September 30, 2004Inventor: Takashi Yoshitomi
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Publication number: 20040155273Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: February 4, 2004Publication date: August 12, 2004Inventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6746929Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: GrantFiled: October 3, 2002Date of Patent: June 8, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6740974Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.Type: GrantFiled: June 24, 2002Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Yoshitomi
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Publication number: 20040070024Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m: and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: October 9, 2003Publication date: April 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20040014331Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.Type: ApplicationFiled: July 15, 2003Publication date: January 22, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi Yoshitomi, Yuichi Nakashima
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Patent number: 6642560Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: June 4, 2002Date of Patent: November 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6617666Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.Type: GrantFiled: March 7, 2002Date of Patent: September 9, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Yuichi Nakashima
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Patent number: 6569987Abstract: To produce meta aramid filaments having a good quality from a polymer solution of a meta aramid produced by a solution polymerization method, with high efficiency, (1) a meta aramid is prepared by polymerization-reacting a aromatic meta-diamine with a aromatic meta-dicarboxylic acid chloride in a polar organic solvent; (2) hydrogen chloride contained in the resultant polymer solution is neutralized with a neutralizing agent containing an alkali metal hydroxide which can react with hydrogen chloride to produce a salt thereof insoluble in the polymerization solvent; (3) the salt deposited from the polymer solution is removed by filtration; (4) the resultant polymer solution is mixed with water and a polar organic amide solvent to prepare a spinning solution; (5) the resultant meta aramid spinning solution is directly extruded in the form of filamentary streams into an aqueous coagulation liquid, to coagulate the extruded filamentary streams of the polymer solution into the form of filaments; (6) the coagulatedType: GrantFiled: June 21, 2001Date of Patent: May 27, 2003Assignee: Teijin LimitedInventors: Akihiro Ohba, Takashi Yoshitomi, Hirozumi Iwasaki, Kotaro Takiue
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Publication number: 20030042521Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: October 3, 2002Publication date: March 6, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masahiko Matsumoto
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Publication number: 20020197815Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.Type: ApplicationFiled: June 24, 2002Publication date: December 26, 2002Inventor: Takashi Yoshitomi
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Publication number: 20020145157Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: June 4, 2002Publication date: October 10, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20020127792Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.Type: ApplicationFiled: March 7, 2002Publication date: September 12, 2002Inventors: Takashi Yoshitomi, Yuichi Nakashima
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Patent number: 6410952Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: April 9, 2001Date of Patent: June 25, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20010045616Abstract: An inductor is formed above an element isolation region in a semiconductor substrate, and a grounded shield layer is interposed between the inductor and element isolation region. The shield layer is formed of high-resistance polysilicon, monocrystalline silicon or amorphous silicon doped with low-concentration impurities whose conductivity type is opposite to that of the semiconductor substrate. An impurity diffusion region which is formed in a well under the element isolation region and whose conductivity type is opposite to that of the well, can be used as the shield layer.Type: ApplicationFiled: June 28, 1999Publication date: November 29, 2001Inventor: TAKASHI YOSHITOMI
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Publication number: 20010042873Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: April 9, 2001Publication date: November 22, 2001Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20010026003Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: March 22, 2001Publication date: October 4, 2001Inventors: Takashi Yoshitomi, Masahiko Matsumoto