Patents by Inventor Takashi Yoshitomi

Takashi Yoshitomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6894331
    Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: May 17, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Tatsuya Ohguro, Ryoji Hasumi, Hideki Kimijima, Takashi Yamaguchi, Masahiro Inohara
  • Patent number: 6864137
    Abstract: A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: March 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Yuichi Nakashima
  • Publication number: 20050001255
    Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 6, 2005
    Inventors: Takashi Yoshitomi, Tatsuya Ohguro, Ryoji Hasumi, Hideki Kimijima, Takashi Yamaguchi, Masahiro Inohara
  • Publication number: 20040188747
    Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.
    Type: Application
    Filed: April 13, 2004
    Publication date: September 30, 2004
    Inventor: Takashi Yoshitomi
  • Publication number: 20040155273
    Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.
    Type: Application
    Filed: February 4, 2004
    Publication date: August 12, 2004
    Inventors: Takashi Yoshitomi, Masahiko Matsumoto
  • Patent number: 6746929
    Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: June 8, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masahiko Matsumoto
  • Patent number: 6740974
    Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: May 25, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Yoshitomi
  • Publication number: 20040070024
    Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m: and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
    Type: Application
    Filed: October 9, 2003
    Publication date: April 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
  • Publication number: 20040014331
    Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 22, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Yoshitomi, Yuichi Nakashima
  • Patent number: 6642560
    Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
  • Patent number: 6617666
    Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Yuichi Nakashima
  • Patent number: 6569987
    Abstract: To produce meta aramid filaments having a good quality from a polymer solution of a meta aramid produced by a solution polymerization method, with high efficiency, (1) a meta aramid is prepared by polymerization-reacting a aromatic meta-diamine with a aromatic meta-dicarboxylic acid chloride in a polar organic solvent; (2) hydrogen chloride contained in the resultant polymer solution is neutralized with a neutralizing agent containing an alkali metal hydroxide which can react with hydrogen chloride to produce a salt thereof insoluble in the polymerization solvent; (3) the salt deposited from the polymer solution is removed by filtration; (4) the resultant polymer solution is mixed with water and a polar organic amide solvent to prepare a spinning solution; (5) the resultant meta aramid spinning solution is directly extruded in the form of filamentary streams into an aqueous coagulation liquid, to coagulate the extruded filamentary streams of the polymer solution into the form of filaments; (6) the coagulated
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: May 27, 2003
    Assignee: Teijin Limited
    Inventors: Akihiro Ohba, Takashi Yoshitomi, Hirozumi Iwasaki, Kotaro Takiue
  • Publication number: 20030042521
    Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.
    Type: Application
    Filed: October 3, 2002
    Publication date: March 6, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masahiko Matsumoto
  • Publication number: 20020197815
    Abstract: A semiconductor device includes a first electrode film, first and second electrode films, first and second connection parts, first and second wirings, and a protective insulating film. The second electrode film opposes the first electrode film. The capacitor insulating film is provided between the first electrode film and the second electrode film. The first and second connection parts are electrically connected to the first and second electrode films, respectively. The first wiring is electrically connected to the first electrode film by the first connection part. The second wiring is electrically connected to the second electrode film by the second connection part. The protective insulating film is provided between the capacitor insulating film and the second electrode film or on the second electrode film.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 26, 2002
    Inventor: Takashi Yoshitomi
  • Publication number: 20020145157
    Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
    Type: Application
    Filed: June 4, 2002
    Publication date: October 10, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
  • Publication number: 20020127792
    Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 12, 2002
    Inventors: Takashi Yoshitomi, Yuichi Nakashima
  • Patent number: 6410952
    Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: June 25, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
  • Publication number: 20010045616
    Abstract: An inductor is formed above an element isolation region in a semiconductor substrate, and a grounded shield layer is interposed between the inductor and element isolation region. The shield layer is formed of high-resistance polysilicon, monocrystalline silicon or amorphous silicon doped with low-concentration impurities whose conductivity type is opposite to that of the semiconductor substrate. An impurity diffusion region which is formed in a well under the element isolation region and whose conductivity type is opposite to that of the well, can be used as the shield layer.
    Type: Application
    Filed: June 28, 1999
    Publication date: November 29, 2001
    Inventor: TAKASHI YOSHITOMI
  • Publication number: 20010042873
    Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
    Type: Application
    Filed: April 9, 2001
    Publication date: November 22, 2001
    Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
  • Publication number: 20010026003
    Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.
    Type: Application
    Filed: March 22, 2001
    Publication date: October 4, 2001
    Inventors: Takashi Yoshitomi, Masahiko Matsumoto