Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

Abstract: A damper mechanism may include a fixed body; a movable body; and a damper member disposed between the fixed body and the movable body so as to be in contact with both of the movable body and the fixed body. The damper member may include a gel member, and a first sheet member joined to a surface of the gel member on a side of one of the movable body and the fixed body.

Abstract: There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once.

Abstract: A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data across drain-source terminals of two or more memory cells that are write targets via bit lines to write simultaneously a plurality of data elements having mutually different data values to the memory cells.

Abstract: An object is to provide a program for a game apparatus for making a plurality of moving objects including a moving object operated by a player to compete in virtual space against each other, in which players are capable of fully using the stage effects specific to a virtual game to enjoy a heated racing game even when they vary in skill. In a program for a game apparatus comprising moving-object operating means, image-information generating means, and image-information outputting means, the program causes a computer to perform a step of producing land-configuration information, a step of monitoring movement information regarding a plurality of moving objects, a step of producing a special area object when results of monitoring meet predetermined requirements, a step of displaying the special area object in such a manner as to be viewable for the player, and a step of allowing another moving object to ride therein.

Abstract: The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction type implantation region provided in a region outside the gate electrode, a sidewall that exposes a top face of the gate electrode and is formed by laminating a sidewall mask oxide layer covering side surfaces, an electron storage nitride layer and a sidewall silicon oxide layer, and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall.

Abstract: There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once.

Abstract: A liquid crystal display apparatus including a glass substrate having a liquid display part formed thereon and a plurality of flexible boards connected to a periphery of the glass substrate. The apparatus also includes a liquid crystal drive IC mounted on each of the flexible boards so as to generate liquid crystal drive signals based on input signals. Additionally, the glass substrate has first internal lines and second internal lines. The first internal lines supply the input signals supplied from a first one of the flexible boards to a second one of the flexible boards, and the second internal lines return the input signals supplied from the first one of the flexible boards back to the first one of the flexible boards without any change.

Abstract: A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data across drain-source terminals of two or more memory cells that are write targets via bit lines to write simultaneously a plurality of data elements having mutually different data values to the memory cells.

Abstract: A MONOS type non-volatile semiconductor memory device has a memory cell array. The memory cell array includes a plurality of pairs of bit line and control line. These bit line-control line pairs are parallel to the channel on the substrate. The memory cell array also includes a plurality of memory cells. Each memory cell has a two-transistor configuration. A certain number of memory cells are disposed between the bit line and control line of each pair. These memory cells are connected in series, and connected with the bit line and control line alternately. The first gate electrode and second gate electrode in the memory cell are formed in strips in a direction perpendicular to the channel.

Abstract: A semiconductor nonvolatile memory has a memory cell array in which each memory cell has a pair of charge traps and each charge trap stores data with at least three possible values. Different data values produce different read current values. To store data, a controller and a voltage supplying unit in the semiconductor nonvolatile memory successively program and verify the charge traps that require programming, using higher programming voltages for data values that must produce lower read currents. This operation is iterated on the charge traps that have not yet attained their necessary read current values, until no such charge traps remain. The programming voltages are set so that all charge traps require substantially the same number of programming iterations, regardless of the data being stored.

Abstract: An object is to provide a program for a game apparatus for making a plurality of moving objects including a moving object operated by a player to compete in virtual space against each other, in which players are capable of fully using the stage effects specific to a virtual game to enjoy a heated racing game even when they vary in skill. In a program for a game apparatus comprising moving-object operating means, image-information generating means, and image-information outputting means, the program causes a computer to perform a step of producing land-configuration information, a step of monitoring movement information regarding a plurality of moving objects, a step of producing a special area object when results of monitoring meet predetermined requirements, a step of displaying the special area object in such a manner as to be viewable for the player, and a step of allowing another moving object to ride therein.

Abstract: A nonvolatile semiconductor memory having an LDD structure includes a control gate located above a channel region, insulating layers formed on the both side surface of the control gate, and I-letter shaped charge-storage layers formed on the insulating layers wherein a bottom surface of the each charge-storage layer are located above the LDD.

Abstract: Source diffusion layers and drain diffusion layers are alternately formed in lateral device forming regions separated by device isolation regions. Control gate electrodes are formed on both sides of each source diffusion layer through gate ONO films interposed therebetween. Gate electrodes are formed over their corresponding side surfaces of the control gate electrodes through inter-gate electrode insulating films interposed therebetween respectively. The control gate electrodes and the gate electrodes are respectively connected in a vertical direction by a source line and word lines on each device isolation region. Further, an intermediate insulating film is formed over the surface of a silicon substrate formed with memory cells, and each lateral drain diffusion layer is connected to a bit line through contacts.

Abstract: A semiconductor nonvolatile memory has a memory cell array in which each memory cell has a pair of charge traps and each charge trap stores data with at least three possible values. Different data values produce different read current values. To store data, a controller and a voltage supplying unit in the semiconductor nonvolatile memory successively program and verify the charge traps that require programming, using higher programming voltages for data values that must produce lower read currents. This operation is iterated on the charge traps that have not yet attained their necessary read current values, until no such charge traps remain. The programming voltages are set so that all charge traps require substantially the same number of programming iterations, regardless of the data being stored.