Abstract: A semiconductor nonvolatile memory has a memory cell array in which each memory cell has a pair of charge traps and each charge trap stores data with at least three possible values. Different data values produce different read current values. To store data, a controller and a voltage supplying unit in the semiconductor nonvolatile memory successively program and verify the charge traps that require programming, using higher programming voltages for data values that must produce lower read currents. This operation is iterated on the charge traps that have not yet attained their necessary read current values, until no such charge traps remain. The programming voltages are set so that all charge traps require substantially the same number of programming iterations, regardless of the data being stored.

Abstract: The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction type implantation region provided in a region outside the gate electrode, a sidewall that exposes a top face of the gate electrode and is formed by laminating a sidewall mask oxide layer covering side surfaces, an electron storage nitride layer and a sidewall silicon oxide layer, and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall.

Abstract: It is an object of the present invention to provide a semiconductor device that enables cost increase to be inhibited and enables cell size to be reduced, and a method for manufacturing the same. A semiconductor device includes a semiconductor substrate, a gate electrode, a first sidewall, and a second sidewall. The gate electrode is formed above the semiconductor substrate. The first sidewall is formed above the semiconductor substrate to be adjacent to the gate electrode. The second sidewall is formed above the semiconductor substrate to face the first sidewall across the gate electrode. The first sidewall includes a first sloping surface. The first sloping surface faces the gate electrode. The first sloping surface slopes so as to close the gap with a second sidewall as it gets closer to the semiconductor substrate. The first sidewall includes a second sloping surface. The second sloping surface faces the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of first wirings disposed above the semiconductor substrate along a first direction, a diffusion layer that is disposed on the surface of the semiconductor substrate so as to extend along a second direction perpendicular to the first direction and which includes a plurality of first diffusion portions overlapping with the plurality of first wirings, a first conductive film that is disposed between adjacent first diffusion layer portions of the plurality of the first diffusion layer portions disposed along the plurality of first wirings, respectively, in a layer between the semiconductor substrate and the plurality of first wirings, and electrically coupled to the plurality of first wirings, a plurality of sidewall portions, each of which is formed on a lateral side of the first conductive film to be disposed between the first conductive film and its adjacent first diffusion layer portion so as to extend along the diffusion layer, and a sec

Abstract: A semiconductor memory device with improved characteristics in a reading operation is disclosed. This semiconductor memory device has: a first diffused region disposed within a semiconductor substrate; a gate dielectric spaced apart from the first diffused region, and overlying the semiconductor substrate; a gate electrode overlying the gate dielectric; a first multilayer disposed between the first diffused region and the gate dielectric, and overlying the semiconductor substrate; and a third diffused region disposed adjacent to the first multilayer within the semiconductor substrate, and doped with dopant at lower concentration than the first diffused region. The first multilayer accumulates a first charge (electron, for example), and subsequently accumulates a second charge (hole, for example) having a polarity that is opposite to the first charge, in a programming operation.

Abstract: Source diffusion layers and drain diffusion layers are alternately formed in lateral device forming regions separated by device isolation regions. Control gate electrodes are formed on both sides of each source diffusion layer through gate ONO films interposed therebetween. Gate electrodes are formed over their corresponding side surfaces of the control gate electrodes through inter-gate electrode insulating films interposed therebetween respectively. The control gate electrodes and the gate electrodes are respectively connected in a vertical direction by a source line and word lines on each device isolation region. Further, an intermediate insulating film is formed over the surface of a silicon substrate formed with memory cells, and each lateral drain diffusion layer is connected to a bit line through contacts.

Abstract: A MONOS type non-volatile semiconductor memory device has a memory cell array. The memory cell array includes a plurality of pairs of bit line and control line. These bit line-control line pairs are parallel to the channel on the substrate. The memory cell array also includes a plurality of memory cells. Each memory cell has a two-transistor configuration. A certain number of memory cells are disposed between the bit line and control line of each pair. These memory cells are connected in series, and connected with the bit line and control line alternately. The first gate electrode and second gate electrode in the memory cell are formed in strips in a direction perpendicular to the channel.

Abstract: A liquid crystal display device converts input signals into liquid crystal drive signals so as to display an image on a liquid crystal panel. A plurality of flexible boards are connected to the liquid crystal panel, each of the flexible boards having a drive IC which converts the input signals into the liquid crystal drive signals. A connection board is connected to the liquid crystal panel so as to supply the input signals to first input lines formed on the liquid crystal panel. Each of the flexible boards has second input signal lines for supplying the input signals to the drive IC; a first end of each of the second input signal lines is connected to a respective one of a first group of the first input signal lines.

Abstract: An operational unit determines, for subfield(s) other than a last subfield of a plurality of subfields constituting a single frame period, based on a difference determined by a data comparison unit, exceeded display data for setting the transmittance of each pixel to a value exceeding a target transmittance corresponding to image data supplied anew. The operational unit also determines, for the last subfield of the single frame period, based on the difference determined by the data comparison unit, target display data for setting the transmittance of each pixel to the target transmittance. An overshoot operation or operations are performed within the single frame period, and each pixel is set to the transmittance corresponding to the image data. This makes it possible to avoid trails occurring in moving image display and enhance the appearance of moving image display with no increase in frame rate.

Abstract: An object of this invention is to provide an image processing apparatus and image processing method capable of reducing a load for drawing, diversifying image representation and smoothing character motion. An image processing means (2) synthesizes background image data (3d) composed of movie image with character data (4d) composed of solid image of polygon data and supplies to a display (6). An image (60) produced by synthesizing the background image (3) with the character (4) is displayed on the display (6). A simple model (5d) composed of three dimensional data for determining the precedence in erasing a negative face between the background image data (3d) and character data (4d) is set in part of the background image data. The image processing means (2) determines a portion in which the character (4) is hidden by the background (3) based on the simple model and erase a corresponding portion. This erase processing enables a screen to be represented three-dimensionally.

Abstract: An operational unit determines, for subfield(s) other than a last subfield of a plurality of subfields constituting a single frame period, based on a difference determined by a data comparison unit, exceeded display data for setting the transmittance of each pixel to a value exceeding a target transmittance corresponding to image data supplied anew. The operational unit also determines, for the last subfield of the single frame period, based on the difference determined by the data comparison unit, target display data for setting the transmittance of each pixel to the target transmittance. An overshoot operation or operations are performed within the single frame period, and each pixel is set to the transmittance corresponding to the image data. This makes it possible to avoid trails occurring in moving image display and enhance the appearance of moving image display with no increase in frame rate.

Abstract: A liquid crystal display device converts input signals into liquid crystal drive signals so as to display an image on a liquid crystal panel. A plurality of flexible boards are connected to the liquid crystal panel, each of the flexible boards having a drive IC which converts the input signals into the liquid crystal drive signals. A connection board is connected to the liquid crystal panel so as to supply the input signals to first input lines formed on the liquid crystal panel. Each of the flexible boards has second input signal lines for supplying the input signals to the drive IC; a first end of each of the second input signal lines is connected to a respective one of a first group of the first input signal lines.

Abstract: A method for establishing electrical connection of a pressure-connector terminal by forming a plurality of divided terminals by providing a plurality of grooves on a connecting surface of a pressure-connector terminal used for TAB connection and COG connection, placing such divided connecting surfaces in contact with a connecting surface of an opposed terminal electrode, imperfectly hardening a bonding material under such condition, deforming a divided terminal by applying pressure and thereafter perfectly hardening the bonding material and a configuration of the pressure-connector terminal are disclosed.