Patents by Inventor Takasuke Hashimoto
Takasuke Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180108609Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.Type: ApplicationFiled: December 15, 2017Publication date: April 19, 2018Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
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Patent number: 9875962Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.Type: GrantFiled: March 13, 2017Date of Patent: January 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida, Kazunori Go, Hiroshi Oe, Noriko Yoshikawa
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Publication number: 20170186689Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
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Patent number: 9632119Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.Type: GrantFiled: September 3, 2014Date of Patent: April 25, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida, Kazunori Go, Hiroshi Oe, Noriko Yoshikawa
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Patent number: 9529022Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.Type: GrantFiled: September 4, 2014Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida
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Patent number: 9245840Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.Type: GrantFiled: October 29, 2014Date of Patent: January 26, 2016Assignee: Renesas Elecronics CorporationInventors: Takasuke Hashimoto, Shinichi Uchida, Yasutaka Nakashiba, Takatsugu Nemoto
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Publication number: 20150061645Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.Type: ApplicationFiled: September 4, 2014Publication date: March 5, 2015Inventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida
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Publication number: 20150061660Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.Type: ApplicationFiled: September 3, 2014Publication date: March 5, 2015Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
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Publication number: 20150048481Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.Type: ApplicationFiled: October 29, 2014Publication date: February 19, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takasuke HASHIMOTO, Shinichi UCHIDA, Yasutaka NAKASHIBA, Takatsugu NEMOTO
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Patent number: 8907460Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.Type: GrantFiled: August 28, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Takasuke Hashimoto, Shinichi Uchida, Yasutaka Nakashiba, Takatsugu Nemoto
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Patent number: 8786048Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.Type: GrantFiled: February 11, 2013Date of Patent: July 22, 2014Assignee: Renesas Electronics CorporationInventors: Mototsugu Okushima, Takasuke Hashimoto
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Publication number: 20140078709Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.Type: ApplicationFiled: August 28, 2013Publication date: March 20, 2014Applicant: Renesas Electronics CorporationInventors: Takasuke HASHIMOTO, Shinichi UCHIDA, Yasutaka NAKASHIBA, Takatsugu NEMOTO
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Publication number: 20130147011Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.Type: ApplicationFiled: February 11, 2013Publication date: June 13, 2013Inventors: Mototsugu OKUSHIMA, Takasuke Hashimoto
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Patent number: 8395234Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.Type: GrantFiled: July 27, 2010Date of Patent: March 12, 2013Assignee: Renesas Electronics CorporationInventors: Mototsugu Okushima, Takasuke Hashimoto
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Patent number: 8310034Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.Type: GrantFiled: May 20, 2010Date of Patent: November 13, 2012Assignee: RENESAS Electronics CorporationInventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
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Publication number: 20110049672Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.Type: ApplicationFiled: July 27, 2010Publication date: March 3, 2011Inventors: Mototsugu OKUSHIMA, Takasuke Hashimoto
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Publication number: 20100314727Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.Type: ApplicationFiled: May 20, 2010Publication date: December 16, 2010Applicant: NEC Electronics CorporationInventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
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Publication number: 20100009510Abstract: A method of manufacturing a semiconductor device including implanting an impurity ion into a predetermined region of a semiconductor layer using a resist film as a mask, wherein in case when a mask data ratio for implanting the impurity ion only into the predetermined region in the resist film is less than a first reference value, a dummy ion implantation region, into which the impurity ion is also implanted in addition to the predetermined region, is added in a region other than the predetermined region so that a mask data ratio becomes larger than a second reference value which is equal to or larger than the first reference value, the mask data ratio indicating a ratio of an opening with respect to an entire region of a reticle region corresponding to the reticle.Type: ApplicationFiled: July 8, 2009Publication date: January 14, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Takasuke Hashimoto
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Patent number: 6680234Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.Type: GrantFiled: August 29, 2002Date of Patent: January 20, 2004Assignee: NEC Electronics CorporationInventor: Takasuke Hashimoto
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Patent number: 6570241Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.Type: GrantFiled: May 25, 2001Date of Patent: May 27, 2003Assignee: NEC Electronics CorporationInventor: Takasuke Hashimoto