Patents by Inventor Takasuke Hashimoto

Takasuke Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180108609
    Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.
    Type: Application
    Filed: December 15, 2017
    Publication date: April 19, 2018
    Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
  • Patent number: 9875962
    Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: January 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida, Kazunori Go, Hiroshi Oe, Noriko Yoshikawa
  • Publication number: 20170186689
    Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
  • Patent number: 9632119
    Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: April 25, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida, Kazunori Go, Hiroshi Oe, Noriko Yoshikawa
  • Patent number: 9529022
    Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida
  • Patent number: 9245840
    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 26, 2016
    Assignee: Renesas Elecronics Corporation
    Inventors: Takasuke Hashimoto, Shinichi Uchida, Yasutaka Nakashiba, Takatsugu Nemoto
  • Publication number: 20150061645
    Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida
  • Publication number: 20150061660
    Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
  • Publication number: 20150048481
    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 19, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takasuke HASHIMOTO, Shinichi UCHIDA, Yasutaka NAKASHIBA, Takatsugu NEMOTO
  • Patent number: 8907460
    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takasuke Hashimoto, Shinichi Uchida, Yasutaka Nakashiba, Takatsugu Nemoto
  • Patent number: 8786048
    Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Mototsugu Okushima, Takasuke Hashimoto
  • Publication number: 20140078709
    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takasuke HASHIMOTO, Shinichi UCHIDA, Yasutaka NAKASHIBA, Takatsugu NEMOTO
  • Publication number: 20130147011
    Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.
    Type: Application
    Filed: February 11, 2013
    Publication date: June 13, 2013
    Inventors: Mototsugu OKUSHIMA, Takasuke Hashimoto
  • Patent number: 8395234
    Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: March 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Mototsugu Okushima, Takasuke Hashimoto
  • Patent number: 8310034
    Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 13, 2012
    Assignee: RENESAS Electronics Corporation
    Inventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
  • Publication number: 20110049672
    Abstract: A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.
    Type: Application
    Filed: July 27, 2010
    Publication date: March 3, 2011
    Inventors: Mototsugu OKUSHIMA, Takasuke Hashimoto
  • Publication number: 20100314727
    Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.
    Type: Application
    Filed: May 20, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
  • Publication number: 20100009510
    Abstract: A method of manufacturing a semiconductor device including implanting an impurity ion into a predetermined region of a semiconductor layer using a resist film as a mask, wherein in case when a mask data ratio for implanting the impurity ion only into the predetermined region in the resist film is less than a first reference value, a dummy ion implantation region, into which the impurity ion is also implanted in addition to the predetermined region, is added in a region other than the predetermined region so that a mask data ratio becomes larger than a second reference value which is equal to or larger than the first reference value, the mask data ratio indicating a ratio of an opening with respect to an entire region of a reticle region corresponding to the reticle.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 14, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takasuke Hashimoto
  • Patent number: 6680234
    Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: January 20, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Takasuke Hashimoto
  • Patent number: 6570241
    Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: May 27, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Takasuke Hashimoto