Patents by Inventor Takatoshi Kameshima
Takatoshi Kameshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11101313Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.Type: GrantFiled: March 23, 2018Date of Patent: August 24, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
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Patent number: 11069637Abstract: Provided is a semiconductor device, a manufacturing method, and an electronic device designed to suppress the occurrence of Cu pumping. The semiconductor device includes a Cu electrode pad serving as a bonding surface for bonding a plurality of semiconductor members together and an electrode via, the electrode via being a connection member that connects the Cu electrode pad to a lower-layer metal. The Cu electrode pad is formed in a location displaced from the electrode via.Type: GrantFiled: October 5, 2017Date of Patent: July 20, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Takatoshi Kameshima
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Publication number: 20210217797Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
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Patent number: 10998369Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: March 23, 2018Date of Patent: May 4, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Publication number: 20210104572Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: ApplicationFiled: March 23, 2018Publication date: April 8, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
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Publication number: 20210104571Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: March 23, 2018Publication date: April 8, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
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Publication number: 20210104570Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance.Type: ApplicationFiled: March 23, 2018Publication date: April 8, 2021Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
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Publication number: 20200243591Abstract: [Object] To further improve performance of a solid-state imaging device. [Solution] There is provided a solid-state imaging device including: a first substrate; a second substrate; and a third substrate that are stacked in this order. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate. The first semiconductor substrate has a pixel unit formed thereon. The pixel unit has pixels arranged thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate. The second semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate. The third semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function.Type: ApplicationFiled: March 23, 2018Publication date: July 30, 2020Inventors: TADASHI IIJIMA, TAKATOSHI KAMESHIMA, IKUE MITSUHASHI, HIROSHI HORIKOSHI, HIDETO HASHIGUCHI, REIJIROH SHOHJI, MINORU ISHIDA, MASAKI HANEDA
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Publication number: 20200105813Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: March 23, 2018Publication date: April 2, 2020Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
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Publication number: 20200105814Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: ApplicationFiled: March 23, 2018Publication date: April 2, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
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Publication number: 20200098815Abstract: [Object] To further improve performance of a solid-state imaging device.Type: ApplicationFiled: March 23, 2018Publication date: March 26, 2020Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
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Publication number: 20200091217Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.Type: ApplicationFiled: March 23, 2018Publication date: March 19, 2020Inventors: HIROSHI HORIKOSHI, MINORU ISHIDA, REIJIROH SHOHJI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, MASAKI HANEDA
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Publication number: 20200035630Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, and an electronic device designed to suppress the occurrence of Cu pumping. A semiconductor device includes: a Cu electrode pad serving as a bonding surface for bonding a plurality of semiconductor members together; and an electrode via, the electrode via being a connection member that connects the Cu electrode pad to a lower-layer metal. The Cu electrode pad is formed in a location displaced from the electrode via. The present disclosure can be applied to, for example, a multilayer solid-state imaging device, such as a CMOS device.Type: ApplicationFiled: October 5, 2017Publication date: January 30, 2020Inventor: TAKATOSHI KAMESHIMA
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Patent number: 9224879Abstract: There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy.Type: GrantFiled: July 19, 2013Date of Patent: December 29, 2015Assignee: Sony CorporationInventor: Takatoshi Kameshima
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Patent number: 8759222Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.Type: GrantFiled: March 1, 2007Date of Patent: June 24, 2014Assignee: Sony CorporationInventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
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Publication number: 20140054739Abstract: There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy.Type: ApplicationFiled: July 19, 2013Publication date: February 27, 2014Inventor: Takatoshi Kameshima
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Patent number: 7897205Abstract: A film forming method is characterized in that the method is provided with a step of introducing a processing gas including inorganic silane gas into a processing chamber, in which a mounting table composed of ceramics including a metal oxide is arranged, and precoating an inner wall of the processing chamber including a surface of the mounting table with a silicon-containing nonmetal thin film; a step of mounting a substrate to be processed on the mounting table precoated with the nonmetal thin film; and a step of introducing a processing gas including organic silane gas into the processing chamber, and forming a silicon-containing nonmetal thin film on a surface of the substrate mounted on the mounting table.Type: GrantFiled: April 7, 2006Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Takatoshi Kameshima, Kohei Kawamura, Yasuo Kobayashi
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Patent number: 7803705Abstract: A dielectric film (91) made of CF is deposited on a substrate. A protective layer comprising an SiCN film (93) is formed on the dielectric film (91). A film (94) serving as a hardmask made of SiCO is deposited on the protective layer by a plasma containing active species of silicon, carbon, and oxygen. When the protective layer is formed, an SiC film (92) is deposited on the dielectric film (91) by a plasma containing active species of silicon and carbon, and thereafter the SiCN film (93) is deposited on the SiC film (92) by a plasma containing active species of silicon, carbon, and nitrogen.Type: GrantFiled: January 13, 2005Date of Patent: September 28, 2010Assignee: Tokyo Electron LimitedInventors: Yasuo Kobayashi, Kenichi Nishizawa, Takatoshi Kameshima, Takaaki Matsuoka
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Patent number: 7602061Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.Type: GrantFiled: August 29, 2007Date of Patent: October 13, 2009Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Tsutomu Shimayama, Takatoshi Kameshima
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Publication number: 20090061092Abstract: A film forming method is characterized in that the method is provided with a step of introducing a processing gas including inorganic silane gas into a processing chamber, in which a mounting table composed of ceramics including a metal oxide is arranged, and precoating an inner wall of the processing chamber including a surface of the mounting table with a silicon-containing nonmetal thin film; a step of mounting a substrate to be processed on the mounting table precoated with the nonmetal thin film; and a step of introducing a processing gas including organic silane gas into the processing chamber, and forming a silicon-containing nonmetal thin film on a surface of the substrate mounted on the mounting table.Type: ApplicationFiled: April 7, 2006Publication date: March 5, 2009Applicant: Tokyo Electron LimitedInventors: Takatoshi Kameshima, Kohei Kawamura, Yasuo Kobayashi